AD9540BCPZ-REEL AD [Analog Devices], AD9540BCPZ-REEL Datasheet - Page 4

• Manufacturer Part Number: AD9540BCPZ-REEL
• Description: 655 MHz Low Jitter Clock Generator
• Manufacturer: AD [Analog Devices]

AD9540
SPECIFICATIONS
AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ T
DRV_R
Table 1.
Parameter
TOTAL SYSTEM JITTER AND PHASE NOISE FOR
105 MHz ADC CLOCK GENERATION CIRCUIT
TOTAL SYSTEM PHASE NOISE FOR 210 MHz
ADC CLOCK GENERATION CIRCUIT
TOTAL SYSTEM TIME JITTER FOR CLOCKS
RF DIVIDER/CML DRIVER EQUIVALENT
INTRINSIC TIME JITTER
RF DIVIDER/CML DRIVER RESIDUAL PHASE NOISE
Converter Limiting Jitter
Resultant SNR
Phase Noise of Fundamental
Phase Noise of Fundamental
155.52 MHz Clock
622.08 MHz Clock
F
F
F
F
F
IN
IN
IN
IN
IN
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
≥1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 Hz
@ 100 Hz
@ 1 kHz
@ 10 kHz
@ 100 kHz
≥1 MHz
@ 10 Hz
@ 100 Hz
@ 1 KHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
>3 MHz
= 414.72 MHz, F
= 1244.16 MHz, F
= 2488.32 MHz, F
= 81.92 MHz, F
= 983.04 MHz, F
SET
= 4.02 kΩ, unless otherwise noted.
OUT
OUT
OUT
OUT
OUT
= 10.24 MHz
= 51.84 MHz
= 122.88 MHz
= 155.52 MHz
= 622.08 MHz
1
Min
Rev. 0 | Page 4 of 32
Typ
720
59.07
80
92
101
110
147
153
79.2
86
95
105
144
151
581
188
136
101
108
120
128
137
145
150
153
115
125
132
142
146
151
153
Max
A
= 25°C), DAC_R
Unit
f
dB
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
f
f
f
f
f
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
S
S
S
S
S
S
rms
rms
rms
rms
rms
rms
SET
= 3.92 kΩ, CP_R
RF Divider R = 8
Test Conditions/Comments
12 kHz to 1.3 MHz bandwidth
12 kHz to 5 MHz bandwidth
R = 8, BW = 12 kHz to 400 kHz
R = 8, BW = 12 kHz to 1.3 MHz
R = 4, BW = 12 kHz to 5 MHz
RF Divider R = 8
SET
= 3.09 kΩ,