AD9540-VCO/PCBZ Analog Devices Inc, AD9540-VCO/PCBZ Datasheet
AD9540-VCO/PCBZ
Specifications of AD9540-VCO/PCBZ
Related parts for AD9540-VCO/PCBZ
AD9540-VCO/PCBZ Summary of contents
Page 1
... Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 CP_RSET CP REF, AMP CHARGE CP_OUT PUMP CLK2 CLK2 DRV_RSET CML OUT0 OUT0 AD9540 IOUT 10 DDS DAC IOUT DAC_RSET ©2006 Analog Devices, Inc. All rights reserved. AD9540 www.analog.com ...
Page 2
... AD9540 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Overview............................................................................. 3 Specifications..................................................................................... 4 Loop Measurement Conditions.................................................. 8 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 12 Typical Application Circuits.......................................................... 17 Application Circuit Descriptions ............................................. 18 Theory of Operation ...................................................................... 19 PLL Circuitry .............................................................................. 19 REVISION HISTORY 2/06—Rev Rev. A Changes to Features Section ...
Page 3
... Extremely fine tuning resolution (steps less than 2.33 µHz) is another feature supported by this device. Information is loaded into the AD9540 via a serial I/O port that has a device write speed of 25 Mbps. The AD9540 frequency divider block can also be programmed to support a spread spectrum mode of operation ...
Page 4
... AD9540 SPECIFICATIONS AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± DRV_R = 4.02 kΩ, unless otherwise noted. SET Table 1. Parameter TOTAL SYSTEM JITTER AND PHASE NOISE FOR 105 MHz ADC CLOCK GENERATION CIRCUIT 1 Converter Limiting Jitter Resultant Signal-to-Noise Ratio (SNR) Phase Noise of Fundamental ...
Page 5
... CP_VDD − 0.5 2 148 133 116 113 1 2700 3 1500 −10 +4 200 1000 Rev Page AD9540 Unit Test Conditions/Comments RF Divider dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz RF Divider dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz MHz mV p-p pF Ω MHz ...
Page 6
... AD9540 Parameter CML OUTPUT DRIVER (OUT0) 5 Differential Output Voltage Swing Maximum Toggle Rate Common-Mode Output Voltage Output Duty Cycle Output Current 6 Continuous Rising Edge Surge Falling Edge Surge Output Rise Time Output Fall Time LOGIC INPUTS (SDI/O, I/O_RESET, RESET, I/O_UPDATE, S0, S1, S2, SYNC_IN) ...
Page 7
... AVDD − 0.50 AVDD + 0. 122 134 143 150 158 160 Rev Page AD9540 Unit Test Conditions/Comments ns ns SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles Bits µA pF dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
Page 8
... AD9540 Parameter 51.84 MHz F OUT @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset > 1 MHz Offset 105 MHz Analog Out @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset 155.52 MHz Analog Out ...
Page 9
... This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev Page AD9540 ...
Page 10
... CS 17 DVDD_I/O 18 SYNC_OUT 19 SYNC_IN/STATUS 20 I/O_UPDATE AGND 1 PIN 1 AVDD 2 INDICATOR AGND 3 AVDD 4 IOUT 5 AD9540 IOUT 6 AVDD 7 TOP VIEW (Not to Scale) AGND DVDD 11 DGND 12 Figure 3. 48-Lead LFCSP Pin Configuration Description Analog Ground. Analog Core Supply (1.8 V). DAC Analog Output. DAC Analog Complementary Output. ...
Page 11
... CML Driver Output Current Set. Program CML output current with a resistor to AGND. DAC Output Current Set. Program DAC output current with a resistor to AGND. The exposed paddle on this package is an electrical connection as well as a thermal enhancement. In order for the device to function properly, the paddle must be attached to analog ground. Rev Page AD9540 ...
Page 12
... AD9540 TYPICAL PERFORMANCE CHARACTERISTICS DELTA 1 [T1] RBW REF LVL –85.94dB VBW 0dBm –2.10420842kHz SWT 0 1 –10 –20 –30 –40 –50 –60 –70 –80 1 –90 –100 CENTER 10.1MHz 5kHz/ Figure 4. DAC Performance: 400 MSPS Clock, 10 MHz kHz Span OUT DELTA 1 [T1] RBW REF LVL – ...
Page 13
... A –10 –20 – –40 –50 –60 –70 –80 –90 –100 STOP 200MHz START 0Hz Rev Page AD9540 DELTA 1 [T1] RBW 100Hz RF ATT 20dB –85.98dB VBW 100Hz –2.90581162kHz SWT 25s UNIT 1 1 5kHz/ SPAN 50kHz Figure 13. DAC Performance: 400 MSPS Clock, ...
Page 14
... AD9540 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k FREQUENCY (Hz) Figure 16. DDS/DAC Residual Phase Noise 400 MHz Clock, 19.7 MHz Output 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 – ...
Page 15
... Figure 27. RF Divider and CML Driver Residual Phase Noise (1966.08 MHz In, 491.52 MHz Out) Rev Page AD9540 100 1k 10k 100k 1M FREQUENCY (Hz) Phase Noise (1240 MHz In, 155 MHz Out) 100 1k 10k 100k 1M FREQUENCY (Hz) ...
Page 16
... AD9540 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k FREQUENCY (Hz) Figure 28. RF Divider and CML Driver Residual Phase Noise (2488 MHz In, 622 MHz Out) 0 –10 –20 –30 –40 –50 –60 – ...
Page 17
... DDS LPF AD9540 Figure 34 Fractional-Divider Loop DDS DAC PHASE FREQUENCY DETECTOR REFIN LPF CHARGE PUMP CLK2 ÷N AD9540 Figure 35. Direct Upconversion of DDS Output Spectrum Rev Page CLOCK1 CLOCK1′ LPF ADCMP563 CML DRIVER CLOCK1 CLOCK2 ADCMP563 VCO ÷R VCO LPF AD9540 ...
Page 18
... CLK2 Figure 36. ISM Band Modulator (LO & Baseband Generation) Direct Upconversion The AD9540 is configured to use the DDS as a precision reference to the PLL. Since the VCO is <655 MHz, it can be fed straight into the phase frequency detector feedback. LO and Baseband Modulation Generation Using the AD9540 PLL section to generate LO and the DDS ...
Page 19
... THEORY OF OPERATION PLL CIRCUITRY The AD9540 includes an RF divider (divide-by-R), a 48-bit DDS core, a 14-bit programmable delay adjustment, a 10-bit DAC (digital-to-analog converter), a phase frequency detector, and a programmable output current charge pump. Incorporat- ing these blocks together, users can generate many useful circuits for clock synthesis. A few simple examples are shown in the Typical Performance Characteristics section ...
Page 20
... AD9540 DDS AND DAC The precision frequency division within the device is accomplished using DDS technology. The DDS can control the digital phase relationships by clocking a 48-bit accumulator. The incremental value loaded into the accumulator, known as the frequency tuning word, controls the overflow rate of the accumulator. Similar to a sine wave completing a 2π ...
Page 21
... Note that the synchronization functions included on the AD9540 control only the timing relationships among different digital clocks. They do not compensate for the analog timing delay on the system clock due to mismatched phase relationships on the input clock, CLK1 (see Figure 38) ...
Page 22
... All data input to the AD9540 is registered on the rising edge of SCLK. All data is driven out of the AD9540 on the falling edge of SCLK. Figure 39 through Figure 42 are useful in understand- ing the general operation of the AD9540 serial port. ...
Page 23
... However, the instruction byte phase of the communication cycle still precedes the data transfer cycle. For MSB first operation, all data written to (or read from) the AD9540 are in MSB first order. If the LSB mode is active, all data written to (or read from) the AD9540 are in LSB first order. ...
Page 24
... SDI/O Open Open Open Input Only PFD REFIN SYNC_CLK Auto Input Cyrstal Out Sync Power- Enable Disable Multiple Down AD9540s Open Open Open Open Clock Driver Falling Edge Control [28:26] RF Divider Clock Clock Driver Input Ratio[22:21] Driver Power- Down 1 Open CP CP Full PD ...
Page 25
... Frequency Tuning Word 5 (FTW5) [47:40] Frequency Tuning Word 5 (FTW5) [39:32] Frequency Tuning Word 5 (FTW5) [31:24] Frequency Tuning Word 5 (FTW5) [23:16] Frequency Tuning Word 5 (FTW5) [15:8] Frequency Tuning Word 5 (FTW5) [7:0] Rev Page AD9540 Bit 2 Bit 1 Bit 0 (LSB) Default Value/ Profile 0x00 ...
Page 26
... AD9540 Register Name (Serial Bit Address) Range Bit 7 (MSB) [63:56] Open 1 Profile Control [55:48] Register 6 [47:40] (PCR6) [39:32] (0x0C) [31:24] [23:16] [15:8] [7:0] 1 Profile [63:56] Open Control [55:48] Register 7 [47:40] (PCR7) [39:32] (0x0D) [31:24] [23:16] [15:8] [7: all cases, Open bits must be written to 0. ...
Page 27
... This control register is comprised of four bytes that must be written during a write operation involving CFR1. CFR1 is used to control various functions, features, and operating modes of the AD9540. The functionality of each bit is described below. In general, the bit is named for the function it serves when the bit is set. ...
Page 28
... CFR1[15 Serial data transfer to the device is in LSB first mode. CFR1[14] SDI/O Input Only (3-Wire Serial Data Mode) The serial port on the AD9540 can act in 2-wire mode (SCLK and SDI/O) or 3-wire mode (SCLK, SDI/O, and SDO). This bit toggles the serial port between these two modes. ...
Page 29
... CFR2 primarily controls analog and timing functions on the AD9540. CFR2[39] DAC Power-Down Bit This bit powers down the DAC portion of the AD9540 and puts it into the lowest power dissipation state. CFR2[39 (default). DAC is powered on and operating. CFR2[39 DAC is powered down and the output high impedance state ...
Page 30
... AD9540 CFR2[24 (default). The lock detect acts as a status indicator (PLL is locked 0 or unlocked 1). CFR2[24 The lock detect acts as a lead-lag indicator the STATUS pin means that the CLK2 pin lags the reference means that the CLK2 pin leads the reference. ...
Page 31
... CP_RSET pin to ground (see the PLL Circuitry section). However possible to multiply the charge pump output current by a value from 1:8 by program- ming these bits. The charge pump output current is scaled by CFR2[2:0] +1. CFR2[2:0] = 000 (default) Scale factor = 1 to CFR2[2:0] = 111 (8). Rev Page AD9540 ...
Page 32
... ORDERING GUIDE Model Temperature Range 1 AD9540BCPZ −40°C to +85°C 1 AD9540BCPZ-REEL7 −40°C to +85°C AD9540/PCB AD9540-VCO/PCB Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.60 MAX 6.75 BSC SQ 0.50 0.40 ...