AD9540BCPZ-REEL AD [Analog Devices], AD9540BCPZ-REEL Datasheet - Page 20

• Manufacturer Part Number: AD9540BCPZ-REEL
• Description: 655 MHz Low Jitter Clock Generator
• Manufacturer: AD [Analog Devices]

AD9540
DDS AND DAC
The precision frequency division within the device is accom-
plished using DDS technology. The DDS can control the digital
phase relationships by clocking a 48-bit accumulator. The
incremental value loaded into the accumulator, known as the
frequency tuning word, controls the overflow rate of the
accumulator. Similar to a sine wave completing a 2π radian
revolution, the overflow of the accumulator is cyclical in nature
and generates a fundamental frequency according to
The instantaneous phase of the sine wave is therefore the output
of the phase accumulator block. This signal may be phase-offset
by programming an additive digital phase that is added to each
phase sample coming out of the accumulator.
These instantaneous phase values are then piped through a
phase-to-amplitude conversion (sometimes called an angle-to-
amplitude conversion or AAC) block. This algorithm follows a
cos(x) relationship, where x is the phase coming out of the
phase offset block, normalized to 2π.
f
o
=
FTW
2
48
×
(
f
s
)
{0
≤ FT
W
≤
2
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47
}
Finally, the amplitude words are piped to a 10-bit DAC. Because
the DAC is a sampled data system, the output is a reconstructed
sine wave that needs to be filtered to take high frequency im-
ages out of the spectrum. The DAC is a current steering DAC
that is AVDD referenced. To get a measurable voltage output,
the DAC outputs must be terminated through a load resistor to
AVDD, typically 50 Ω. At positive full scale, IOUT sinks no cur-
rent and the voltage drop across the load resistor is 0. However,
the IOUT output sinks the DAC’s programmed full-scale output
current, causing the maximum output voltage drop across the
load resistor. At negative full-scale, the situation is reversed and
IOUT sinks the full-scale current (and generates the maximum
drop across the load resistor), while IOUT sinks no current
(and generates no voltage drop). At midscale, the outputs sink
equal amounts of current, generating equal voltage drops.