AD9540BCPZ-REEL AD [Analog Devices], AD9540BCPZ-REEL Datasheet - Page 12

• Manufacturer Part Number: AD9540BCPZ-REEL
• Description: 655 MHz Low Jitter Clock Generator
• Manufacturer: AD [Analog Devices]

AD9540
Table 3. 48-Lead LFCSP Pin Function Descriptions
Pin No.
1, 3, 8, 26, 30,
34, 37, 43, 49
2, 4, 7, 27, 38,
44, 48
5
6
9
10
11, 25
12, 24
13
14
15
16
17
18
19
20
21, 22, 23
28
29
31
32
33
35
36
39
40
41
42
45
46
47
NOTE: The exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. In order for the device
to function properly, the paddle must be attached to analog ground.
Mnemonic
AGND
AVDD
IOUT
IOUT
I/O_RESET
RESET
DVDD
DGND
SDO
SDI/O
SCLK
CS
DVDD_I/O
SYNC_OUT
SYNC_IN/STATUS
I/O_UPDATE
S0, S1, S2
CLK1
CLK1
VCML
OUT0
OUT0
VCP
CP
REFIN
REFIN
CLK2
CLK2
CP_RSET
DRV_RSET
DAC_RSET
Master RESET. Clears all accumulators and returns all registers to their default values (active high).
Charge Pump Current Set (Program Charge Pump Current with a Resistor to AGND).
Description
Analog Ground.
Analog Core Supply (1.8 V).
DAC Analog Output.
DAC Analog Complementary Output.
Resets the serial port when synchronization is lost in communications but does not reset the de-
vice itself (active high). When not being used, this pin should be forced low, because it floats to the
threshold value.
Digital Core Supply (1.8 V).
Digital Ground.
Serial Data Output. Used only when device is programmed for 3-wire serial data mode.
Serial Data I/O. When the part is programmed for 3-wire serial data mode, this is input only; in
2-wire mode, it serves as both the input and output.
Serial Data Clock. Provides the clock signal for the serial data port.
Active Low Signal That Enables Shared Serial Buses. When brought high, the serial port ignores the
serial data clocks.
Digital Interface Supply (3.3 V).
Synchronization Clock Output.
Bidirectional Dual Function Pin. Depending on device programming, this pin is either the DDS’s
synchronization input (allows alignment of multiple subclocks), or the PLL lock detect output signal.
This input pin, when set high, transfers the data from the I/O buffers to the internal registers on the
rising edge of the internal SYNC_CLK, which can be observed on SYNC_OUT.
Clock Frequency and Delay Select Pins. Specify one of eight clock frequency/delay profiles.
RF Divider and Internal Clock Input.
RF Divider and Internal Clock Input.
CML Driver Supply Pin.
CML Driver Complementary Output.
CML Driver Output.
Charge Pump Supply Pin (3.3 V). To minimize noise on the charge pump, isolate this supply from
DVDD_I/O.
Charge Pump Output.
Phase Frequency Detector Reference Input.
Phase Frequency Detector Reference Complementary Input.
Phase Frequency Detector Oscillator (Feedback) Complementary Input.
Phase Frequency Detector Oscillator (Feedback) Input.
CML Driver Output Current Set (Program CML Output Current with a Resistor to AGND).
DAC Output Current Set (Program DAC Output Current with a Resistor to AGND).
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