AD9540BCPZ-REEL AD [Analog Devices], AD9540BCPZ-REEL Datasheet - Page 24

• Manufacturer Part Number: AD9540BCPZ-REEL
• Description: 655 MHz Low Jitter Clock Generator
• Manufacturer: AD [Analog Devices]

AD9540
REGISTER MAP AND DESCRIPTION
Table 5. Register Map
Register
Name (Serial
Address)
Control
Function
Register 1
(CFR1) (0x00)
Control
Function
Register 2
(CFR2) (0x01)
Rising Delta
Frequency
Tuning Word
(RDFTW)
(0x02)
Falling Delta
Frequency
Tuning Word
(FDFTW)
(0x03)
Rising Sweep
Ramp Rate
(RSRR) (0x04)
Falling Sweep
Ramp Rate
(FSRR) (0x05)
1
In all cases, Open bits must be written to 0.
Bit
Range
<31:24>
<23:16>
<15:8>
<7:0>
<39:32>
<31:24>
<23:16>
<15:8>
<7:0>
<23:16>
<15:8>
<7:0>
<23:16>
<15:8>
<7:0>
<15:8>
<7:0>
<15:8>
<7:0>
Bit 7 (MSB)
Open
LOAD SRR @
I/O_UPDATE
LSB First
Dig. Power-
Down
DAC Power-
Down
Clock Driver Rising Edge <31:29>
RF Divider
Power-
Down
Open
1
1
Divider M Control <15:12>
Bit 6
Open
Auto-
Clear
Freq.
Accum.
SDI/O
Input
Only
PFD
Input
Power-
Down
Open
Open
RF Divider Ratio
<22:21>
1
1
1
Bit 5
Open
Auto-
Clear
Phase
Accum.
Open
REFIN
Cyrstal
Enable
Open
CP
Polarity
Falling Delta Frequency Tuning Word <23:16>
Rising Delta Frequency Tuning Word <23:16>
Falling Delta Frequency Tuning Word <15:8>
Rising Delta Frequency Tuning Word <15:8>
Falling Delta Frequency Tuning Word <7:0>
Rising Delta Frequency Tuning Word <7:0>
1
1
1
Rev. 0 | Page 24 of 32
Rising Sweep Ramp Rate <15:8>
Rising Sweep Ramp Rate <15:8>
Rising Sweep Ramp Rate <7:0>
Rising Sweep Ramp Rate <7:0>
Bit 4
Open
Enable
Sine Out-
put
Open
SYNC_CLK
Out Dis-
able
Open
Clock
Driver
Power-
Down
CP Full PD
Clock Driver Falling Edge Control
1
1
1
<28:26>
Bit 3
Open
Clear
Freq.
Accum.
Open
Auto
Sync
Multiple
AD9540s
Open
CP Quick
PD
Clock Driver Input
Select <19:18>
1
1
1
Bit 2
Open
Clear
Phase
Accum.
Open
Software
Manual
Sync
Open
Divider N Control <11:8>
1
1
1
CP Current Scale <2:0>
Bit 1
Open
Open
Open
Hardware
Manual
Sync
Internal
Band Gap
Power-
Down
PLL Lock
Detect
Enable
Slew Rate
Control
1
1
1
Bit 0 (LSB)
STATUS_Error
Open
Open
High Speed
Sync Enable
Internal CML
Driver
DRV_RSET
PLL Lock
Detect Mode
RF Div CLK1
Mux Bit
1
1
Default
Value/
Profile
0x00
0x00
0x00
0x00
0x00
0x00
0x78
0x00
0x07
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00