AD9540BCPZ-REEL AD [Analog Devices], AD9540BCPZ-REEL Datasheet - Page 22

• Manufacturer Part Number: AD9540BCPZ-REEL
• Description: 655 MHz Low Jitter Clock Generator
• Manufacturer: AD [Analog Devices]

AD9540
SERIAL PORT OPERATION
An AD9540 serial data-port communication cycle has two
phases. Phase 1 is the instruction cycle, which is the writing of
an instruction byte to the AD9540, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9540 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the
register being accessed.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9540. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9540
and the system controller. The number of bytes transferred
during Phase 2 of the communication cycle is a function of the
.
SCLK
SDI/O
SCLK
SDI/O
SCLK
SDI/O
SCLK
SDI/O
SDO
CS
CS
CS
CS
I
I
7
7
I
I
7
7
I
I
6
6
I
I
6
6
INSTRUCTION CYCLE
INSTRUCTION CYCLE
I
INSTRUCTION CYCLE
I
INSTRUCTION CYCLE
Figure 37. 3-Wire Serial Port Read Timing—Clock Stall Low
Figure 39. 2-Wire Serial Port Read Timing−Clock Stall High
5
5
I
I
5
5
Figure 36. Serial Port Write Timing—Clock Stall Low
Figure 38. Serial Port Write Timing−Clock Stall High
I
I
4
4
I
I
4
4
I
I
3
3
I
I
3
3
I
I
2
2
I
I
2
2
Rev. 0 | Page 22 of 32
I
I
1
1
I
I
1
1
I
I
0
0
I
I
0
0
D
D
O 7
7
register being accessed. For example, when accessing Control
Function Register 2, which is four bytes wide, Phase 2 requires that
four bytes be transferred. If accessing a frequency tuning word,
which is six bytes wide, Phase 2 requires that six bytes be trans-
ferred. After transferring all data bytes per the instruction, the
communication cycle is completed.
At the completion of any communication cycle, the AD9540
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9540 is registered on the rising edge of
SCLK. All data is driven out of the AD9540 on the falling edge
of SCLK. Figure 36 through Figure 39 are useful in understand-
ing the general operation of the AD9540 serial port.
D
7
D
O 7
D
D
6
O 6
D
D
O 6
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
6
D
D
5
O 5
DON'T CARE
D
D
O 5
5
D
D
4
O 4
D
D
O 4
4
D
D
3
O 3
D
D
O 3
D
3
D
2
O 2
D
D
O 2
2
D
D
1
O 1
D
D
O 1
1
D
0
D
O 0
D
O 0
D
0