AD9540BCPZ-REEL AD [Analog Devices], AD9540BCPZ-REEL Datasheet - Page 28

• Manufacturer Part Number: AD9540BCPZ-REEL
• Description: 655 MHz Low Jitter Clock Generator
• Manufacturer: AD [Analog Devices]

AD9540
CFR1 <15> LSB First Serial Data Mode
The serial data transfer to the device can be either MSB first or
LSB first. This bit controls that operation.
CFR1<15> = 0 (default). Serial data transfer to the device is in
MSB first mode.
CFR1<15> = 1. Serial data transfer to the device is in LSB first mode.
CFR1<14> SDI/O Input Only (3-Wire Serial Data Mode)
The serial port on the AD9540 can act in 2-wire mode (SCLK
and SDI/O) or 3-wire mode (SCLK, SDI/O, and SDO). This bit
toggles the serial port between these two modes.
CFR1<14> = 0 (default). Serial data transfer to the device is in
2-wire mode. The SDI/O pin is bidirectional.
CFR1<14> = 1. Serial data transfer to the device is in 3-wire
mode. The SDI/O pin is input only.
CFR1<13:8> Open
Unused locations. Write a Logic 0.
CFR1<7> Digital Power-Down
This bit powers down the digital circuitry not directly related
to the I/O port. The I/O port functionality is not suspended,
regardless of the state of this bit.
CFR1<7> = 0 (default). Digital logic operating as normal.
CFR1<7> = 1. All digital logic not directly related to the I/O
port is powered down. Internal digital clocks are suspended.
CFR1<6> Phase Frequency Detector Input Power-Down
This bit controls the input buffers on the phase frequency
detector. It provides a way to gate external signals from the
phase frequency detector.
CFR1<6> = 0 (default). Phase frequency detector input buffers
are functioning normally.
CFR1<6> = 1. Phase frequency detector input buffers are
powered down, isolating the phase frequency detector from the
outside world.
CFR1<5> REFIN Crystal Enable
The AD9540 phase frequency detector has an on-chip oscillator
circuit. When enabled, the reference input to the phase fre-
quency detector (REFIN/ PLLREF ) can be driven by a crystal.
CFR1<5> = 0 (default). The phase frequency detector reference
input operates as a standard analog input.
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CFR1<5> = 1. The reference input oscillator circuit is enabled,
allowing the use of a crystal for the reference of the phase
frequency detector.
CFR1<4> SYNC_CLK Disable
If synchronization of multiple devices is not required, the spec-
tral energy resulting from this signal can be reduced by gating
the output buffer off. This function gates the internal clock ref-
erence SYNC_CLK (SYSCLK ÷ 4) off of the SYNC_OUT pin.
CFR1<4> = 0 (default). The SYNC_CLK signal is present on the
SYNC_OUT pin and is ready to be ported to other devices.
CFR1<4> = 1. The SYNC_CLK signal is gated off, putting the
SYNC_OUT pin into a high impedance state.
CFR1<3> Automatic Synchronization
One of the synchronization modes of the AD9540 forces the
DDS core to derive the internal reference from an external ref-
erence supplied on the SYNC_IN pin. For details on synchroni-
zation modes for the DDS core, see the Synchronization Modes
for Multiple Devices section.
CFR1<3> = 0 (default). The automatic synchronization function
of the DDS core is disabled.
CFR1<3> = 1. The automatic synchronization function is on.
The device is slaved to an external reference and adjusts the
internal SYNC_CLK to match the external reference, which is
supplied on the SYNC_IN input.
CFR1<2> Software Manual Synchronization
Rather than relying on the part to automatically synchronize the
internal clocks, the user can program the part to advance the
internal SYNC_CLK one system clock cycle. This bit is self
clearing and can be set multiple times.
CFR1<2> = 0 (default). The SYNC_CLK stays in the current
timing relationship to SYSCLK.
CFR1<2> = 1. The SYNC_CLK advances the rising and falling
edges by one SYSCLK cycle. This bit is then self-cleared.
CFR1<1> Hardware Manual Synchronization
Similar to the software manual synchronization (CFR1<2>),
this function enables the user to advance the SYNC_CLK rising
edge by one system clock period. This bit enables the
SYNC_IN/STATUS pin as a digital input. Once enabled, every
rising edge on the SYNC_IN input advances the SYNC_CLK by
one SYCLK period. While enabled, the STATUS signal is not
available on an external pin. However, loop out-of-lock events
trigger a flag in the control register (CFR1<24>).