AD9540BCPZ-REEL AD [Analog Devices], AD9540BCPZ-REEL Datasheet
AD9540BCPZ-REEL
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AD9540BCPZ-REEL Summary of contents
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FEATURES Excellent intrinsic jitter performance 25 Mb/s write-speed serial I/O control 200 MHz phase frequency detector inputs 655 MHz programmable input dividers for the phase fre- quency detector (÷M, ÷N) { 1..16} (bypassable) Programmable RF divider (÷R) {R ...
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AD9540 TABLE OF CONTENTS Product Overview............................................................................. 3 Specifications..................................................................................... 4 Loop Measurement Conditions.................................................. 9 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Typical Performance Characteristics ........................................... 13 Typical Application Circuits.......................................................... 18 Application Circuit Descriptions ............................................. 18 ...
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PRODUCT OVERVIEW The AD9540 is Analog Devices’ first dedicated clocking product specifically designed to support the extremely stringent clock- ing requirements of the highest performance data converters. The device features high performance PLL circuitry, including a flexible 200 MHz phase ...
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AD9540 SPECIFICATIONS AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± DRV_R = 4.02 kΩ, unless otherwise noted. SET Table 1. Parameter TOTAL SYSTEM JITTER AND PHASE NOISE FOR 105 MHz ...
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Parameter F = 1966.08 MHz 491.52 MHz IN OUT @ 100 kHz @ 10 kHz @ 100 kHz @ 1 MHz >3 MHz F = 2488 MHz 622 MHz IN ...
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AD9540 Parameter CML OUTPUT DRIVER (OUT0) 5 Differential Output Voltage Swing Maximum Toggle Rate Common-Mode Output Voltage Output Duty Cycle Output Current 6 Continuous Rising Edge Surge Falling Edge Surge Output Rise Time Output Fall Time LOGIC INPUTS (SDI/O, I/O_RESET, ...
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Parameter I/O Update to SYNC_CLK Setup Time PS<2:0> to SYNC_CLK Setup Time Latencies/Pipeline Delays I/O Update to DAC Frequency Change I/O Update to DAC Phase Change PS<2:0> to DAC Frequency Change PS<2:0> to DAC Phase Change I/O Update to CP_OUT ...
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AD9540 Parameter 51.84 MHz F OUT @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset > 1 MHz Offset 105 MHz Analog Out @ 10 Hz Offset @ 100 ...
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LOOP MEASUREMENT CONDITIONS 622 MHz OC-12 Clock VCO = Sirenza 190-640T Reference = Wenzel 500-10116 (30.3 MHz) Loop Filter = 10 kHz BW, 60° Phase Margin C1 = 170 nF 14.4 Ω 5.11 µ ...
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AD9540 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Analog Supply Voltage (AVDD Digital Supply Voltage (DVDD Digital I/O Supply Voltage 3.6 V (DVDD_I/0) 3.6 V Charge Pump Supply Voltage (CPVDD) Maximum Digital Input Voltage −0.5 V ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I/O_RESET NOTE: The exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. For the device to function properly, the paddle must be attached to analog ground. 48 ...
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AD9540 Table 3. 48-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic 26, 30, AGND 34, 37, 43 27, 38, AVDD 44 IOUT 6 IOUT 9 I/O_RESET 10 RESET 11, 25 DVDD ...
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TYPICAL PERFORMANCE CHARACTERISTICS DELTA 1 [T1] RBW 100Hz REF LVL –85.94dB VBW 100Hz 0dBm –2.10420842kHz SWT 0 1 –10 –20 –30 –40 –50 –60 –70 –80 1 –90 –100 CENTER 10.1MHz 5kHz/ Figure 4. AD9540 DAC Performance: 400 MSPS Clock, ...
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AD9540 DELTA 1 [T1] RBW 100Hz –83.72dB VBW 100Hz REF LVL –2.70541082kHz SWT 0dBm 0 1 –10 –20 –30 –40 –50 –60 –70 –80 1 –90 –100 CENTER 100.1MHz 5kHz/ Figure 10. AD9540 DAC Performance: 400 MSPS Clock, 100 MHz ...
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FREQUENCY (Hz) Figure 16. AD9540 DDS/DAC Residual Phase Noise 400 MHz Clock, 19.7 MHz Output 0 –10 –20 ...
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AD9540 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k FREQUENCY (Hz) Figure 22. RF Divider and CML Driver Residual Phase Noise (410.4 MHz In, 51.3 MHz ...
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FREQUENCY (Hz) Figure 28. RF Divider and CML Driver Residual Phase Noise (2488 MHz In, 622 MHz ...
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AD9540 TYPICAL APPLICATION CIRCUITS 25MHz CRYSTAL EXTERNAL REFERENCE APPLICATION CIRCUIT DESCRIPTIONS Dual Clock Configuration: AD9540 Configured in a Dual-Clock Configuration In this loop 16, and The DDS tuning word is also equals ...
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GENERAL DESCRIPTION PLL CIRCUITRY The AD9540 includes an RF divider (divide-by-R), a 48-bit DDS core, a 14-bit programmable delay adjustment, a 10-bit DAC, a phase frequency detector, and a programmable output current charge pump. Incorporating these blocks together, users can ...
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AD9540 DDS AND DAC The precision frequency division within the device is accom- plished using DDS technology. The DDS can control the digital phase relationships by clocking a 48-bit accumulator. The incremental value loaded into the accumulator, known as the ...
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MODES OF OPERATION SELECTABLE CLOCK FREQUENCIES AND SELECT- ABLE EDGE DELAY Because the precision driver is implemented using a DDS possible to store multiple clock frequency words to enable externally switchable clock frequencies. The phase accumulator runs at ...
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AD9540 SERIAL PORT OPERATION An AD9540 serial data-port communication cycle has two phases. Phase 1 is the instruction cycle, which is the writing of an instruction byte to the AD9540, coincident with the first eight SCLK rising edges. The instruction ...
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INSTRUCTION BYTE The instruction byte contains the following information: Table R/ R/Wb—Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte ...
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AD9540 REGISTER MAP AND DESCRIPTION Table 5. Register Map Register Name (Serial Bit Address) Range Bit 7 (MSB) 1 Control <31:24> Open Function <23:16> LOAD SRR @ Register 1 I/O_UPDATE (CFR1) (0x00) <15:8> LSB First <7:0> Dig. Power- Down Control ...
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Register Name Bit Bit 7 (Serial Address) Range (MSB) Profile Control <63:56> Register 0 (PCR0) <55:48> (0x06) <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Profile Control <63:56> Register 1 (PCR1) <55:48> (0x07) <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Profile Control <63:56> ...
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AD9540 Register Name (Serial Address) Bit Bit 7 Range (MSB) Profile Control <63:56> Register 4 (PCR4) <55:48> (0x0A) <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Profile Control <63:56> Register 5 (PCR5) <55:48> (0x0B) <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Profile Control ...
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CONTROL FUNCTION REGISTER DESCRIPTIONS Control Function Register 1 (CFR1) This control register is comprised of four bytes, which must be written during a write operation involving CFR1. CFR1 is used to control various functions, features, and operating modes of the ...
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AD9540 CFR1 <15> LSB First Serial Data Mode The serial data transfer to the device can be either MSB first or LSB first. This bit controls that operation. CFR1<15> (default). Serial data transfer to the device is in ...
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CFR1<1> (default). The hardware manual synchronization function is disabled. Either the part is outputting the STATUS (CFR1<3> using the SYNC_IN to slave the SYNC_CLK signal to an external reference provided on SYNC_IN (CFR1<3> ...
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AD9540 CFR2<24> (default). The lock detect acts as a status indica- tor (PLL is locked 0 or unlocked 1). CFR2<24> The lock detect acts as a lead-lag indicator the STATUS pin means that ...
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CFR2<7:6> Open Unused locations. Write a Logic 0. CFR2<5> CP Polarity This bit sets the polarity of the charge pump in response to a ground referenced or a supply referenced VCO. CFR2<5> (default). The charge pump is configured ...
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... SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9540BCPZ −40°C to +85°C 1 AD9540BCPZ-REEL −40°C to +85°C AD9540/PCB Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective owners. 7.00 BSC SQ ...