AD9540/PCB Analog Devices Inc, AD9540/PCB Datasheet
AD9540/PCB
Specifications of AD9540/PCB
Related parts for AD9540/PCB
AD9540/PCB Summary of contents
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FEATURES Excellent intrinsic jitter performance 200 MHz phase frequency detector inputs 655 MHz programmable input dividers for the phase frequency detector (÷M, ÷N) { 16} (bypassable) Programmable RF divider (÷ ...
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AD9540 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Overview............................................................................. 3 Specifications..................................................................................... 4 Loop Measurement Conditions.................................................. 8 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... ...
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PRODUCT OVERVIEW The AD9540 is Analog Devices’ first dedicated clocking product specifically designed to support the extremely stringent clocking requirements of the highest performance data converters. The device features high performance PLL (phase- locked loop) circuitry, including a flexible 200 ...
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AD9540 SPECIFICATIONS AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± DRV_R = 4.02 kΩ, unless otherwise noted. SET Table 1. Parameter TOTAL SYSTEM JITTER AND PHASE NOISE FOR 105 MHz ...
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Parameter F = 1966.08 MHz 491.52 MHz IN OUT @ 100 kHz @ 10 kHz @ 100 kHz @ 1 MHz >3 MHz F = 2488 MHz 622 MHz IN ...
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AD9540 Parameter CML OUTPUT DRIVER (OUT0) 5 Differential Output Voltage Swing Maximum Toggle Rate Common-Mode Output Voltage Output Duty Cycle Output Current 6 Continuous Rising Edge Surge Falling Edge Surge Output Rise Time Output Fall Time LOGIC INPUTS (SDI/O, I/O_RESET, ...
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Parameter I/O_Update to SYNC_OUT Setup Time PS[2:0> to SYNC_OUT Setup Time Latencies/Pipeline Delays I/O_Update to DAC Frequency Change I/O_Update to DAC Phase Change PS[2:0] to DAC Frequency Change PS[2:0] to DAC Phase Change I/O_Update to CP_OUT Scaler Change I/O_Update to ...
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AD9540 Parameter 51.84 MHz F OUT @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset > 1 MHz Offset 105 MHz Analog Out @ 10 Hz Offset @ 100 ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Analog Supply Voltage (AVDD Digital Supply Voltage (DVDD Digital I/O Supply Voltage 3.6 V (DVDD_I/O) Charge Pump Supply Voltage 3.6 V (CP_VDD) Maximum Digital Input Voltage −0 ...
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AD9540 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I/O_RESET RESET Table 3. Pin Function Descriptions Pin No. Mnemonic 26, 30, AGND 34, 37, 43 27, 38, AVDD 44 IOUT 6 IOUT 9 I/O_RESET 10 ...
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Pin No. Mnemonic 21, 22, 23 S0, S1 CLK1 29 CLK1 31, 35 CP_VDD 32 OUT0 33 OUT0 36 CP_OUT 39 REFIN 40 REFIN 41 CLK2 42 CLK2 45 CP_RSET 46 DRV_RSET 47 DAC_RSET Paddle Exposed Paddle Description ...
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AD9540 TYPICAL PERFORMANCE CHARACTERISTICS DELTA 1 [T1] RBW REF LVL –85.94dB VBW 0dBm –2.10420842kHz SWT 0 1 –10 –20 –30 –40 –50 –60 –70 –80 1 –90 –100 CENTER 10.1MHz 5kHz/ Figure 4. DAC Performance: 400 MSPS Clock, 10 MHz ...
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DELTA 1 [T1] RBW 100Hz –83.72dB VBW 100Hz REF LVL –2.70541082kHz SWT 25s 0dBm 0 1 –10 –20 –30 –40 –50 –60 –70 –80 1 –90 –100 CENTER 100.1MHz 5kHz/ Figure 10. DAC Performance: 400 MSPS Clock, 100 MHz F ...
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AD9540 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k FREQUENCY (Hz) Figure 16. DDS/DAC Residual Phase Noise 400 MHz Clock, 19.7 MHz Output 0 –10 –20 –30 ...
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FREQUENCY (Hz) Figure 22. RF Divider and CML Driver Residual Phase Noise (410.4 MHz In, 51.3 MHz ...
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AD9540 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k FREQUENCY (Hz) Figure 28. RF Divider and CML Driver Residual Phase Noise (2488 MHz In, 622 MHz ...
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TYPICAL APPLICATION CIRCUITS PHASE FREQUENCY 25MHz DETECTOR/CHARGE PUMP CRYSTAL ÷M ÷N AD9540 EXTERNAL REFERENCE REFIN 400MHz CP_OUT VCO LPF CLK2 CML DRIVER ÷R DAC DDS Figure 32. Dual Clock Configuration PHASE FREQUENCY DETECTOR ÷M REFIN 622MHz CHARGE VCO ÷N PUMP ...
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AD9540 25MHz CRYSTAL APPLICATION CIRCUIT DESCRIPTIONS Dual Clock Configuration In this loop 16, and The DDS (direct digital synthesizer) tuning word is also equal to ¼, so that the frequency of CLOCK1’ ...
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THEORY OF OPERATION PLL CIRCUITRY The AD9540 includes an RF divider (divide-by-R), a 48-bit DDS core, a 14-bit programmable delay adjustment, a 10-bit DAC (digital-to-analog converter), a phase frequency detector, and a programmable output current charge pump. Incorporat- ing these ...
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AD9540 DDS AND DAC The precision frequency division within the device is accomplished using DDS technology. The DDS can control the digital phase relationships by clocking a 48-bit accumulator. The incremental value loaded into the accumulator, known as the frequency ...
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MODES OF OPERATION SELECTABLE CLOCK FREQUENCIES AND SELECTABLE EDGE DELAY Because the precision driver is implemented using a DDS possible to store multiple clock frequency words to enable externally switchable clock frequencies. The phase accumulator runs at a ...
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AD9540 SERIAL PORT OPERATION An AD9540 serial data port communication cycle has two phases. Phase 1 is the instruction cycle, writing an instruction byte to the AD9540, coincident with the first eight SCLK rising edges. The instruction byte provides the ...
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INSTRUCTION BYTE The instruction byte contains the following information. MSB R/ R/Wb—Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. ...
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AD9540 REGISTER MAP AND DESCRIPTION Table 4. Register Map Register Name (Serial Bit Address) Range Bit 7 (MSB) 1 Control [31:24] Open Function [23:16] Load SRR @ Register 1 I/O_UPDATE (CFR1) (0x00) [15:8] LSB First [7:0] Digital Power- Down Control ...
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Register Name (Serial Bit Address) Range Bit 7 (MSB) [63:56] Open 1 Profile Control [55:48] Register 0 [47:40] (PCR0) [39:32] (0x06) [31:24] [23:16] [15:8] [7:0] 1 Profile [63:56] Open Control [55:48] Register 1 [47:40] (PCR1) [39:32] (0x07) [31:24] [23:16] [15:8] ...
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AD9540 Register Name (Serial Bit Address) Range Bit 7 (MSB) [63:56] Open 1 Profile Control [55:48] Register 6 [47:40] (PCR6) [39:32] (0x0C) [31:24] [23:16] [15:8] [7:0] 1 Profile [63:56] Open Control [55:48] Register 7 [47:40] (PCR7) [39:32] (0x0D) [31:24] [23:16] ...
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CONTROL REGISTER BIT DESCRIPTIONS Control Function Register 1 (CFR1) This control register is comprised of four bytes that must be written during a write operation involving CFR1. CFR1 is used to control various functions, features, and operating modes of the ...
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AD9540 CFR1[15 (default). Serial data transfer to the device is in MSB first mode. CFR1[15 Serial data transfer to the device is in LSB first mode. CFR1[14] SDI/O Input Only (3-Wire Serial Data Mode) The serial ...
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CFR1[ (default). The hardware manual synchronization function is disabled. Either the part is outputting the STATUS (CFR1[ using the SYNC_IN to slave the SYNC_CLK signal to an external reference provided on SYNC_IN (CFR1[3] ...
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AD9540 CFR2[24 (default). The lock detect acts as a status indicator (PLL is locked 0 or unlocked 1). CFR2[24 The lock detect acts as a lead-lag indicator the STATUS pin means that the ...
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CFR2[7:6] Open Unused locations. Write a Logic 0. CFR2[5] CP Polarity This bit sets the polarity of the charge pump in response to a ground referenced or a supply referenced VCO. CFR2[ (default). The charge pump is configured ...
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... ORDERING GUIDE Model Temperature Range 1 AD9540BCPZ −40°C to +85°C 1 AD9540BCPZ-REEL7 −40°C to +85°C AD9540/PCB AD9540-VCO/PCB Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.60 MAX 6.75 BSC SQ 0.50 ...