h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 624

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 21 Power-Down Modes
21.7
When the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR = 0, the
LSON bit in LPWRCR = 1, and the PSS bit in TCSR (WDT1) = 1, CPU operation shifts to
subsleep mode.
In subsleep mode, the CPU stops and peripheral modules other than WDT0 and WDT1 also stop.
The contents of the CPU internal registers and on-chip RAM data, and the states of on-chip
peripheral modules other than the SCI, A/D converter, motor control PWM, and HCAN, and the
states of I/O ports are retained.
Subsleep mode is canceled by any interrupt (interrupts from on-chip peripheral modules, NMI pin,
or IRQ5 to IRQ0 pins), or signals at the RES or STBY pin.
When an interrupt occurs, subsleep mode is canceled and interrupt exception handling starts.
For an IRQ5 to IRQ0 interrupt, subsleep mode is not canceled if the corresponding enable bit has
been cleared to 0. For an interrupt from an on-chip peripheral module, if the interrupt enable
register has been set to disable the reception of that interrupt or is masked by the CPU, subsleep
mode is not canceled.
For canceling subsleep mode by the RES pin, see section 21.4, Software Standby Mode.
When the STBY pin is driven low, a transition is made to hardware standby mode.
21.8
CPU operation shifts to subactive mode when the SLEEP instruction is executed in high-speed
mode with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1, the LSON bit = 1, and
the PSS bit in TCSR (WDT1) = 1. When an interrupt occurs in watch mode, and if the LSON bit
in LPWRCR is 1, a transition is made to subactive mode. If an interrupt occurs in subsleep mode,
a transition is made to subactive mode.
In subactive mode, the CPU operates at low speed on the subclock, and the program is executed
one after another. Peripheral modules other than WDT0 and WDT1 are also stopped.
When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SCKCR must be set to 0.
Subactive mode is canceled by the SLEEP instruction or signals at the RES or STBY pin.
Rev. 2.00 Dec. 05, 2005 Page 586 of 724
REJ09B0200-0200
Subsleep Mode
Subactive Mode