h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 29

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 13.8 Example of SCI Operation in Reception
Figure 13.9 Sample Serial Reception Data Flowchart (1) .......................................................... 382
Figure 13.9 Sample Serial Reception Data Flowchart (2) .......................................................... 383
Figure 13.10 Example of Communication Using Multiprocessor Format
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 387
Figure 13.12 Example of SCI Operation in Reception
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 389
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 390
Figure 13.14 Data Format in Synchronous Communication (For LSB-First) ............................ 391
Figure 13.15 Sample SCI Initialization Flowchart ..................................................................... 392
Figure 13.16 Sample SCI Transmission Operation in Clocked Synchronous Mode .................. 394
Figure 13.17 Sample Serial Transmission Flowchart ................................................................. 395
Figure 13.18 Example of SCI Operation in Reception ............................................................... 396
Figure 13.19 Sample Serial Reception Flowchart ...................................................................... 397
Figure 13.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ...... 399
Figure 13.21 Schematic Diagram of Smart Card Interface Pin Connections.............................. 400
Figure 13.22 Normal Smart Card Interface Data Format ........................................................... 401
Figure 13.23 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 401
Figure 13.24 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 402
Figure 13.25 Receive Data Sampling Timing in Smart Card Mode
Figure 13.26 Retransfer Operation in SCI Transmit Mode......................................................... 406
Figure 13.27 TEND Flag Generation Timing in Transmission Operation.................................. 406
Figure 13.28 Example of Transmission Processing Flow........................................................... 407
Figure 13.29 Retransfer Operation in SCI Receive Mode .......................................................... 408
Figure 13.30 Example of Reception Processing Flow................................................................ 409
Figure 13.31 Timing for Fixing Clock Output Level.................................................................. 410
Figure 13.32 Clock Halt and Restart Procedure ......................................................................... 411
Figure 13.33 Sample Transmission using DTC in Clocked Synchronous Mode........................ 415
Figure 13.34 Sample Flowchart for Mode Transition during Transmission............................... 416
Figure 13.35 Pin States during Transmission in Asynchronous Mode (Internal Clock)............. 417
Figure 13.36 Pin States during Transmission in Clocked Synchronous Mode
Figure 13.37 Sample Flowchart for Mode Transition during Reception .................................... 418
Figure 13.38 Operation when Switching from SCK Pin to Port Pin........................................... 419
Figure 13.39 Operation when Switching from SCK Pin to Port Pin
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 380
(Transmission of Data H'AA to Receiving Station A) .......................................... 385
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 388
(Using Clock of 372 Times the Transfer Rate) ..................................................... 404
(Internal Clock) ..................................................................................................... 417
(Example of Preventing Low-Level Output)......................................................... 420
Rev. 2.00 Dec. 05, 2005 Page xxix of xxxviii