h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 26

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Bus Controller (BSC)
Figure 7.1 Block Diagram of Bus Controller.............................................................................. 104
Figure 7.2 Area Divisions........................................................................................................... 112
Figure 7.3 Access Sizes and Data Alignment Control (8-Bit Access Space) ............................. 115
Figure 7.4 Access Sizes and Data Alignment Control (16-bit Access Space) ............................ 116
Figure 7.5 Bus Timing for 8-Bit, 2-State Access Space ............................................................. 118
Figure 7.6 Bus Timing for 8-Bit, 3-State Access Space ............................................................. 119
Figure 7.7 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)............. 120
Figure 7.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access).............. 121
Figure 7.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) .................................. 122
Figure 7.10 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)........... 123
Figure 7.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access)............ 124
Figure 7.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ................................ 125
Figure 7.13 Example of Wait State Insertion Timing................................................................. 126
Figure 7.14 Example of Burst ROM Access Timing (AST0 = 1 and BRSTS0 = 1) .................. 128
Figure 7.15 Example of Burst ROM Access Timing (AST0 = 0 and BRSTS1 = 0) .................. 129
Figure 7.16 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) ............ 130
Figure 7.17 Example of Idle Cycle Operation (Write after Read) .............................................. 131
Figure 7.18 Relationship between Chip Select (CS) and Read (RD) ......................................... 132
Figure 7.19 Example of Timing when Write Data Buffer Function is Used .............................. 133
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC ............................................................................................. 138
Figure 8.2 Block Diagram of DTC Activation Source Control .................................................. 145
Figure 8.3 Location of DTC Register Information in Address Space......................................... 146
Figure 8.4 Flowchart of DTC Operation .................................................................................... 149
Figure 8.5 Memory Mapping in Normal Mode .......................................................................... 150
Figure 8.6 Memory Mapping in Repeat Mode ........................................................................... 151
Figure 8.7 Memory Mapping in Block Transfer Mode .............................................................. 153
Figure 8.8 Chain Transfer Operation.......................................................................................... 154
Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ..................... 155
Figure 8.10 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2) ...................................... 156
Figure 8.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 156
Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.1 Block Diagram of TPU............................................................................................ 233
Figure 10.2 Example of Counter Operation Setting Procedure .................................................. 268
Figure 10.3 Free-Running Counter Operation ............................................................................ 269
Figure 10.4 Periodic Counter Operation..................................................................................... 270
Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match.............. 270
Rev. 2.00 Dec. 05, 2005 Page xxvi of xxxviii