h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 153

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In externally expanded
mode, the space excluding the on-chip RAM and internal I/O registers is external address space.
The on-chip RAM is enabled when the RAME bit is set to 1 in the system control register
(SYSCR); when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding
addresses are in external address space.
Only the basic bus interface can be used for area 7.
7.5
The basic bus interface enables direct connection of ROM, SRAM, and so on.
7.5.1
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external address space, controls
whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
8-Bit Access Space: Figure 7.3 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word access is performed as two byte accesses,
and a longword access, as four byte accesses.
Basic Bus Interface
Data Size and Data Alignment
Figure 7.3 Access Sizes and Data Alignment Control (8-Bit Access Space)
Byte size
Word size
Longword
size
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
D15
Upper data bus
Rev. 2.00 Dec. 05, 2005 Page 115 of 724
D8 D7
Lower data bus
Section 7 Bus Controller (BSC)
REJ09B0200-0200
D0