h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 168

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Bus Controller (BSC)
7.7
7.7.1
When this LSI accesses external address space, it can insert a 1-state idle cycle (T
cycles in the following two cases: (1) when read accesses in different areas occur consecutively
and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle, it is
possible, for example, to avoid data collisions between memory with a long output floating time
(such as ROM) and high-speed memory, I/O interfaces, and so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit is set to 1 in BCRH, an idle cycle is inserted at the start of the second read cycle.
Figure 7.16 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Rev. 2.00 Dec. 05, 2005 Page 130 of 724
REJ09B0200-0200
CS* (area A)
CS* (area B)
Note: * The CS signal is generated outside the LSI.
Address bus
Idle Cycle
Operation
Data bus
RD
φ
(a) No idle cycle insertion
(ICIS1 = 0)
T
1
Bus cycle A
Long output floating time
Figure 7.16 Example of Idle Cycle Operation
T
2
(Consecutive Reads in Different Areas)
T
3
Bus cycle B
T
1
T
2
Data collision
CS* (area A)
CS* (area B)
Address bus
Data bus
RD
φ
T
1
Bus cycle A
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
T
2
T
3
Idle cycle
T
Bus cycle B
i
T
i
) between bus
1
T
2