cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 48

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

RESET
G_T1/EI
CPD_IE
TCLK_I/O
CMUX[2:0]
02—CLAD Configuration (CLAD_CR)
FREE
29380-DSH-001-B
CLK_OE
FREE
7
Global Reset
configuration registers to their default values for all four ports. Also, several output pins are
three-stated. RESET is self-clearing bit. After RESET is complete, the following is true:
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Global Clock Mode
in a mode which insures the minimum output jitter on the CLK1544 output or the CLK 2048
output.
Clock Output Enable
outputs.
CLAD Phase Detector Error Interrupt Enable
[CSTAT; addr 06], to generate an interrupt request.
Transmit Clock Input/Output
CLAD Multiplexer Select
detector if FREE = 0 [CLAD_CR; addr 02]. The source can be the receive recovered clock
output (RCKO) from any of the four channels or the CLADI input pin.
Free-Run CLAD
controlled oscillator (NCO) to free-run based on the 10 MHz REFCKI input clock accuracy.
RSCALE[2]
0 = CLK2048 output jitter minimized
1 = CLK1544 output jitter minimized
0 = Clock outputs are three-stated
1 = Clock outputs are enabled
0 = Interrupt disabled
1 = Interrupt enabled
0 = TCLK[1:4] pins are inputs
1 = TCLK[1:4] pins are outputs
000 = CLADI pin
001 = RCKO[1] from channel #1
010 = RCKO[2] from channel #2
011 = RCKO[3] from channel #3
100 = RCKO[4] from channel #4
0 = normal (closed loop) CLAD operation
1 = free run (open loop) NCO operation
Digital receiver outputs (RPOSO[1:4], RNEGO[1:4], RCKO[1:4]) are three-stated.
Transmitter line outputs (XTIP[1:4], XRING[1:4]) are three-stated.
CLK1544, CLK2048, and CLADO clock outputs are three-stated.
Transmitter clocks, TCLK[1:4] are configured as inputs.
All interrupt sources are disabled.
All configuration registers are set to default values.
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Preliminary Information / Mindspeed Proprietary and Confidential
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RSCALE[1]
When written to 1, initiates an internal global reset process which sets all
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Disables the CLAD phase detector in the CLAD, which forces the numerically
5
—
Mindspeed Technologies
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This bit selects one of two CLAD operating modes. The CLAD can operate
Determines output state of CLK1544, CLK2048, and CLADO clock
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Selects the CLAD reference clock source input to the CLAD phase
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RSCALE[0]
Determines whether TCLK[1:4] pins are inputs or outputs.
4
LFGAIN[3]
—
3
Enables CLAD loss of lock detector, CPD_INT
®
LFGAIN[2]
2
LFGAIN[1]
1
Registers
LFGAIN[0]
0
R/W
40