cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 29

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

enabled globally for all channels by pulling the UNIPOLAR pin low. In Host Mode, unipolar operation is enabled per
channel by writing a 1 to register bit UNIPOLAR [RLIU_CR; addr n1].
2.4.2
If enabled, the TZCS encoder encodes unipolar transmit data on TDATI with B8ZS (T1) or HDB3 (E1) line coding.
In T1 mode, eight consecutive 0s are replaced with 000VB0VB; and in E1 mode, four consecutive 0s are replaced
with X00V; where B is a normal AMI pulse, V is a bipolar violation, and X is a Don't Care. These are standard T1
and E1 line code options.
ZCS encoding (and decoding) can be enabled only if the digital interface mode is unipolar. In Host Mode, TZCS
encoding (and RZCS decoding) is enabled for each channel by setting the ZCS [RLIU_CR; addr n1] register bit to
1. In Hardware Mode, ZCS encoding/decoding is controlled globally for all channels by pulling the ZCS pin high.
For the Hardware Mode pin definition, see
2.4.3
Transmit data from the TZCS encoder can be routed to the JAT before going to the AIS Generator. The JAT
attenuates clock and data jitter from the transmit inputs or from the receiver if Remote Line Loopback (RLL) is
active. The JAT can be placed in the receive path or transmit path, but not both simultaneously. If the JAT is placed
in the transmit path, the jitter attenuated clock becomes the transmit clock for downstream circuits.
In Host Mode, the JAT is configured for each channel independently and is put in the transmit path by setting the
JEN register bit to 1 and the JDIR register bit to 0 [JAT_CR; addr n0]. In Hardware Mode, the JAT is configured for
all channels globally using the JSEL(2:0) and JDIR pins. For pin definitions, see
characteristics, see
2.4.4
The transmit data can be replaced with unframed all 1s for transmitting the alarm indication signal (AIS). This
includes replacing data supplied from TPOSI[n]/TNEGI[n] pins and from the receiver during RLL. AIS transmission
does not affect transmit data that is looped back to the receiver during Local Digital Loopback (LDL). This allows
LDL to be active simultaneously with the transmission of AIS. AIS is used to maintain a valid signal on the line and
to inform downstream equipment that the transmit data source has been lost. AIS transmission can be done
manually or automatically when loss of transmit clock is detected. A clock monitor circuit allows manual or
automatic switching of the transmit clock to an alternate AIS clock.
In Hardware Mode, AIS can be controlled only manually by pulling the TAIS [n] hardware pin low. If TCLK[n] is
present, then it is used to transmit AIS. If TCLK[n] is not present (for two clock periods), the alternate AIS clock on
either TACKI (T1 Mode) or EACKI (E1 Mode) is used. The AIS transmit clock switches back to TCLK[n] when the
TCLK[n] signal returns.
In Host Mode, AIS can be transmitted using the TAIS [n] hardware pins or the TAIS register bit, or automatically by
enabling the AUTO_AIS register bit. AIS clock switching can be enabled by using the AISCLK register bit. Setting
AISCLK to 1 forces the use of the alternate AIS clock on either TACKI (T1 Mode) or EACKI (E1 Mode) pins when
transmitting AIS. If AUTO_AIS is set to 1, AIS is automatically transmitted when the clock monitor detects loss of
clock on TCLK[n]. When using automatic AIS transmission, the user should also enable the AISCLK bit and
provide an alternate clock source to ensure that AIS will be transmitted. CLAD output clocks CLK2048 and
CLK1544 can be connected externally to EACKI and TACKI alternate AIS clock inputs for this purpose. Setting
register bit TAIS_PE to 1 disables the TAIS register bit and allows manual transmission of AIS using the TAIS [n]
hardware pins. See LIU_CTL [addr n3] in
29380-DSH-001-B
TZCS Encoder
Transmit Jitter Attenuator
All 1s AIS Generator
Figure
Preliminary Information / Mindspeed Proprietary and Confidential
2-10; and for more information on loopbacks, see
Mindspeed Technologies
Chapter
Table
1-1.
3, and
Table
1-1.
®
Section
Chapter
2.5.
1; for JAT transfer
Circuit Description
21