cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 21

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

Figure 2-2.
2.2.4
The CX28380 supports three reset methods: power-on reset, hard reset initiated by the RESET pin, and soft reset
initiated by the RESET bit in the Global Configuration Register [GCR; addr 01]. In Host Mode, all three reset
methods produce the same results as listed below. In Hardware Mode, power-on reset and hard reset produce the
same results as shown, and soft reset is not applicable. After RESET is complete, the following is true:
29380-DSH-001-B
8380_007
Host Serial Port Signals
SCLK
SCLK
SDO
SDO
SDI
SDI
CS
CS
Reset
Preliminary Information / Mindspeed Proprietary and Confidential
R/W
R/W
Digital receiver outputs (RPOSO[1:4] and
RNEGO[1:4], RCKO[1:4]) are enabled;
RLOS[1:4] outputs are logic high, SDO output
is logic low)
Transmitter line outputs (XTIP[1:4] and
XRING[1:4]) are enabled (controlled by
CLK1544, CLK2048, and CLADO clock
outputs are enabled.
A0
A0
Address/Control Byte
Address/Control Byte
A1
Mindspeed Technologies
A1
Hardware Mode
A2
A2
A3
A3
A4
A4
Read Timing
Write Timing
A5
A5
A6
A6
XOE
D0
D0
).
®
D1
D1
Digital receiver outputs (RPOSO[1:4] and
RNEGO[1:4], RCKO[1:4]) are three-stated;
RLOS[1:4] outputs are logic high, SDO output is
logic low).
Transmitter line outputs (XTIP[1:4] and
XRING[1:4]) are three-stated.
CLK1544, CLK2048, and CLADO clock outputs
are three-stated.
D2
D2
Register Data Byte
Register Data Byte
D3
D3
Host Mode
D4
D4
D5
D5
D6
D6
Circuit Description
D7
D7
13