cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 15

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

Table 1-1.
29380-DSH-001-B
RESET
UNIPOLAR
ZCS
CLK_POL
PTS(2:0)
HTERM
IRQ
JSEL(2:0)
JDIR
JATERR[1:4]
Pin Label
Hardware Signal Definitions (3 of 5)
Hardware Reset
Unipolar Mode Select
Zero Code
Suppression Select
Rx Clock Polarity
Select
Transmit Pulse
Template Select
Transmitter Hardware
Termination
Interrupt Request
or
Transmit DPM
Jitter Attenuator
Select
Jitter Attenuator
Direction
Jitter Attenuator
Error
Signal Name
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
Hardware Control Signals (continued)
I/O
O
I
I
I
I
I
I
I
I
O
P
P
P
P
P
P
P
P
D
Active low asynchronous hardware reset. A falling edge forces registers to their
default, power-up state. Output pins are forced to the high impedance state while
RESET is asserted. RESET is not mandatory at power-up because an internal
power-on reset circuit performs an identical function.
Applicable only in Hardware Mode. A low signal on UNIPOLAR configures all
RPOSO outputs and TPOSI inputs to operate with unipolar, NRZ- formatted data.
In this mode, RNEGO reports BPVs and TNEGI is not used. A high signal on
UNIPOLAR configures all channels’ RPOSO/RNEGO and TPOSI/TNEGI interfaces
to operate with bipolar, dual-rail, NRZ formatted data.
Applicable only in Hardware Mode. A high signal on ZCS enables the transmit ZCS
encoder and the receive ZCS decoder if unipolar mode is enabled (UNIPOLAR =
1). In Bipolar Mode (UNIPOLAR = 0), the ZCS encoder and decoder are disabled
and ZCS is ignored.
Applicable only in Hardware Mode. Low sets RPOSO/RNEGO to be output on the
falling edge of RCKO. High sets RPOSO/RNEGO to be output on the rising edge of
RCKO.
Applicable only in Hardware Mode. The PTS(2:0) control bus selects the transmit
pulse template and the line rate (T1 or E1) globally for all channels. See the
description of HTERM in this table and transmit pulse configurations in
Applicable only in Hardware Mode. If an external transmit termination resistor is
used to meet return loss specifications, a transformer with a 1:2 turns ratio is
used and HTERM is set high to allow the transmitter to compensate for the
increased load. See the Transmitter section of this table and
8
Active low, open drain output. In Host Mode, IRQ indicates one or more pending
interrupt requests ([ISR; addr n6] and [CSTAT; addr 06]). In Hardware Mode,
Transmit DPM (IRQ) is the logical NOR of the four internal transmitter driver
performance monitor outputs.
Applicable only in Hardware Mode. The JSEL and JDIR pins determine the JAT
configuration. JSEL(2:0) enables and selects the JAT depth as shown in the table
below. SDI/JSEL(2) and CS /JSEL(1) are dual function pins.
JSEL(2:0)
Applicable only in Hardware Mode. JDIR determines the path in which the JAT is
inserted. If JDIR is high, the JAT (if enabled) is placed in the receive path; if low,
the JAT (if enabled) is placed in the transmit path. See the description for
JSEL(2:0). SCLK/JDIR is a dual function pin.
elastic store. JATERR(1) / SDO is a dual function pin.
A high on JATERR indicates an overflow or underflow error in the jitter attenuator
for transmitter termination configuration options.
000
001
010
011
100
111
JAT Mode
Disable JAT
8 bits
16 bits
32 bits
64 bits
128 bits
®
Definition
Pin Descriptions
Tables 2-4
through
Table
2-3.
2-
7