cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 42

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

Circuit Description
6. Switch to normal, non-free-run, mode if desired.
Many RSCALE and VSCALE values other than those shown in
Table 2-11
are applicable. For instance, an
alternate configuration for an input reference frequency of 2048 kHz is displayed in
Table
2-12.
Table 2-12.
Sample Alternate Configuration
Phase Compare
CLAD Reference
CLADV
RSCALE
Frequency
VSCALE
VSEL
(kHz)
(kHz)
(kHz)
2048
001
1024
011
8192
0100
RSCALE is a programmable frequency divider which scales the CLAD reference clock frequency before it is
applied to the CLAD’s phase detector. Similarly, VSCALE scales the CLAD’s internal feedback clock, CLADV.
These two clocks must have the same frequency (no greater than 4.096 MHz) at the phase detector’s inputs for the
CLAD’s loop to properly lock. The rule is:
(CLAD reference freq.) ÷ (RSCALE factor) = (CLADV freq.) ÷ (VSCALE factor)
<4.096 MHz
The RSCALE and VSCALE fields determine the degree of clock division which is done on the reference and
variable signals into the CLAD’s phase detector. They must always be set to produce the same (nominal) rate into
the phase detector. Furthermore, they must be set to produce a compare frequency of no greater than 4.096 MHz.
Increasing the RSCALE/VSCALE settings lowers the compare frequency, thereby lowering the 3 dB point of the
jitter transfer curve.
The LFGAIN field in the [CLAD-CR; addr 0Z] is one of the settings which influences the CLAD’s responsiveness.
High values allow the CLAD to react more quickly (by raising the 3 dB point of its jitter transfer curve) while low
values cause the CLAD to react more slowly.
®
Mindspeed Technologies
29380-DSH-001-B
34
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