cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 39

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

2.7
The CLAD uses an input clock reference at a particular frequency (8 kHz to 16,384 kHz) to synthesize output
clocks at a different frequency (8 kHz to 16,384 kHz). The CLAD outputs are frequency-locked to the selected
timing reference. The CLAD can operate with input reference frequencies at multiples and submultiples of T1 or E1
line rates.
Figure 2-11. CLAD Block Diagram
2.7.1
In Hardware Mode, the CLAD input timing reference is supplied from an 8 KHz clock on the CLADI pin. The CLAD
can be set in free-run mode by removing the clock from CLADI (pull high or low). If clock edges are not present on
CLADI, an internal clock monitor automatically switches the timing reference to use the 10 MHz, REFCKI
reference. When clock edges are sensed on CLADI, the reference is switched back to CLADI.
In Host Mode, the CLAD input timing reference can be selected from six sources. The source can be the received
recovered clock output (RCKO[n]) from any of the four channels, the CLADI input pin, or the 10 MHz, REFCKI input
(free-run mode). The CLAD reference is configured by writing to the CMUX[2:0] bits in the Global Control Register
[GCR; addr 01]. Free-run mode is selected by writing 1 to the FREE bit in the CLAD Configuration Register
[CLAD_CR; addr 02]. The CLAD will also free-run if CLADI source is selected and there are no clock edges
present on CLADI. Note also that the external 10 MHz (REFCKI) clock is always required.
29380-DSH-001-B
Figure 2-11
CLADI
Labels in brackets [ ] refer
to register bits.
Refer to the following registers:
Global Configuration; addr 01
CLAD Configuration; addr 02
CLAD Frequency Select; addr 03
CLAD Phase Detector Scale Factor; addr 04
CLAD Status; addr 06
RCKO[1]
RCKO[2]
RCKO[3]
RCKO[4]
Clock Rate Adapter
Inputs
Device I/O Pin
illustrates the CLAD block diagram.
Monitor
Clock
Preliminary Information / Mindspeed Proprietary and Confidential
÷ [RSCALE] Factor
÷ [VSCALE] Factor
CLADR
CLADV
Detector
Mindspeed Technologies
Phase
Clock Rate Adapter (CLAD)
[LFGAIN]
Loop
Filter
13
[G_T1/E1]
[CPD_IE]
Divider Chain
[FREE]
NCO
®
CLAD Control/
32.768 MHz
2.048 MHz
1.544 MHz
14
Status
10 MHz
[CLK_OE]
[CPDERR]
[CPD_INT]
Circuit Description
CLK2048
CLK1544
CLADO
CLK32
REFCKI
31