cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 26

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

Table 2-1.
2.3.2.3
In Host Mode, the receiver allows interfacing to network test (MON) points which are resistively attenuated by 20
dB with resistors in series with receive Tip and Ring signals. Bridge operation is enabled by setting register bit
ATTN [addr n1] to 1.
2.3.2.4
The Receive Loss of Signal (RLOS) Detector monitors both consecutive 0s and signal level. Receive Analog Loss
Of Signal (RALOS) is declared when RTIP/RRING input signal amplitude is a certain level (RALOS level) below the
nominal receive level for 1–2 ms. See
level are detected.
In Host Mode, RALOS real time status is reported in the ALARM [addr n5] register; and an interrupt status bit is
available in the ISR [addr n6] register. Also, RALOS is indicated on the RLOS [n] pin, which is the logical NOR of the
RLOS[n] status and RALOS[n] status.
RLOS is declared when 100 (T1) or 32 (E1) consecutive bit times with no pulses are detected. RLOS status is
cleared when pulses are received with at least 12.5% pulse density (during a period of 192 bit times starting with
the receipt of a pulse) and where no occurrences of 100 or 32 consecutive bits with no pulses are detected. In Host
Mode, RLOS real time status is reported in the ALARM register [addr n5]; and an interrupt status bit is available in
the ISR register [addr n6]. Also, RLOS is indicated by a 0 level on the RLOS [n] pin, which is the logical NOR of the
RLOS[n] status and RALOS[n] status.
2.3.3
2.3.3.1
The Receive Phase Lock Loop (RPLL) recovers the line rate clock from the data slicer dual-rail outputs. The RPLL
generates a recovered clock that tracks jitter in the data and sustains the data-to-clock phase relationship in the
absence of incoming pulses. The RPLL is a digital PLL which adjusts its output phase in 1/64 unit interval (UI)
steps. Consequently, the RPLL adds approximately 0.016 UI peak-to-peak jitter to the recovered receive clock.
During loss of signal (RLOS or RALOS), the RPLL maintains an output clock signal and smoothly transitions to a
nominal line rate frequency determined by the CLAD input reference (selected by CMUX [GCR; addr 01] or FREE
[CLAD_CR; addr 02]). If the CLAD reference is the recovered received clock from a channel which has detected
RLOS, the CLAD outputs and the recovered received clock enter a “hold-over” state to maintain the average
frequency that was present just before the RLOS was detected.
2.3.3.2
Figure 2-9
enabled in the receive path with each JAT elastic store size. The jitter tolerance of the clock and data recovery
circuit alone (not including the JAT) is illustrated by the curve labeled with “Typical Receiver Tolerance with JAT
Disabled.” The receiver meets jitter tolerance specifications TR62411, G.823, and G.824. In addition, the receiver
29380-DSH-001-B
FOOTNOTE:
(1) SENS = 1 for E1 – 75 not applicable.
Settings
illustrates the receiver’s jitter tolerance for all jitter attenuator (JAT) configurations: JAT disabled and JAT
Line Compatible Modes
Bridge Mode
Loss of Signal Detectors
Clock Recovery
Phase Lock Loop
Jitter Tolerance
Preliminary Information / Mindspeed Proprietary and Confidential
Line Mode
Mindspeed Technologies
Table
2-1. RALOS status is cleared as soon as pulses above the RALOS
Sensitivity
®
RALOS
Circuit Description
RLOS
18