cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 36

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

2.5.1
Local Analog Loopback (LAL) causes the transmit data and clock inputs (TPOSI/TNEGI and TCLK) to be looped
back to the receiver outputs (RPOSO/RNEGO and RCKO). This loopback connects an internal copy of the analog
transmit signal (XTIP and XRING outputs) to the receiver input, so that virtually all of the device circuitry can be
tested. While LAL is active, transmit data continues to be transmitted on XTIP and XRING, but RTIP and RRING
inputs are ignored. Applying a high on the XOE pin when Local Analog Loopback is active disables the transmitter
outputs and causes an RLOS.
2.5.2
Local Digital Loopback (LDL) causes the transmit data and clock inputs (TPOSI/TNEGI and TCLK) to be looped
back to the receiver outputs (RPOSO/RNEGO and RCKO). This loopback includes the JAT (if enabled) but does
not include the line transmit and receive circuitry. Consequently, XTIP and XRING transmitter outputs are
unaffected, and receiver RTIP and RRING inputs remain connected to the line to monitor for RLOS. Also, the AIS
(all 1s) generator is not included in the loopback path so that AIS can be transmitted toward the line while
simultaneously providing a local loopback.
2.5.3
Remote Line Loopback (RLL) causes the received data on RTIP/RRING line inputs to be looped back and re-
transmitted on XTIP/XRING line outputs. This loopback includes all receive and transmit circuitry and the JAT, if it is
enabled, but does not include the ZCS decoder and encoder. The receiver outputs (RPOSO/RNEGO and RCKO)
continue to output received data; transmit inputs (TPOSI/TNEGI and TCLK) are ignored.
2.6
The jitter attenuator (JAT) attenuates jitter in the receive or transmit path, but not both simultaneously. The JAT path
configuration and elastic store depth is controlled by the JDIR and JSEL(2:0) pins in Hardware Mode or by the
JEN, JDIR, JCENTER, and JSIZE[2:0] bits in the Jitter Attenuator Configuration register [JAT_CR; addr n0] in Host
Mode. The JAT can also be completely disabled.
The elastic store is configurable using the JSEL(2:0) pins or the JSIZE[2:0] bits in the JAT_CR register. The elastic
store sizes available are 8, 16, 32, 64, and 128 bits. The 64-bit elastic store depth is sufficient to meet jitter
tolerance requirements, and when the selected clock reference is frequency-locked. The larger elastic store depths
allow greater accumulated phase offsets. For example, the 128-bit depth can tolerate up to
phase offset. Because the elastic store is a fixed size, it can overflow and under-run. If either of these conditions
occurs, a Jitter Attenuator Elastic Store Limit Error (JATERR) is reported. In Hardware Mode, JATERR[n] pins are
provided, and in Host Mode, the JERR bit in the Interrupt Status Register [ISR; addr n6] is set.
The elastic store is a circular buffer with independent read and write pointers. These pointers can be initialized
manually using JCENTER in the JAT_CR register. JCENTER resets the write pointer and forces the elastic store
read pointer.
The dejittered receiver recovered clock is output on the RCKO[n] pin if the JAT is configured in the receive path.
The receiver input clock and data jitter tolerance and jitter transfer meet TR 62411-1990.
illustrate jitter tolerance and JAT transfer characteristics.
29380-DSH-001-B
Local Analog Loopback
Local Digital Loopback
Remote Line Loopback
Jitter Attenuator
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
®
Figures 2-9
±
64 bits of accumulated
Circuit Description
and
2-10
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