cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 35

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

2.4.6.2
The transmitter analog outputs, XTIP[n] and XRING[n], are enabled per channel by pulling the XOE [n] pins low and
are three-stated by pulling the XOE [n] pins high. In Host Mode, the PDN [TLIU_CR; addr n2] register bit also
controls the XTIP[n] and XRING[n] outputs. A device RESET sets the PDN bits, thereby disabling XTIP[n] and
XRING[n]. User software must clear PDN to enable the transmitter outputs.
deactivated, XOE [n] controls the transmitter outputs.
2.4.7
2.4.7.1
The transmitter output pulse is monitored and a short circuit is detected when the amplitude falls below an
internally determined threshold after counting 64 pulses. The short circuit state deactivates when the amplitude
rises above a second threshold for 64 pulses.
When a short is detected, the line driver current is reduced to less than 50 mA RMS, as measured on the line side
of the transformer. Typically, a short circuit detection is caused by a transmit cable short circuit or by a transmission
line transient current surge. In Host Mode, short circuit activation sets the TSHORT bit in the Alarm Status register
[ALARM; addr n5] and in the Interrupt Status Register [ISR; addr n6]. Short circuit detection and current limiting
continue to function in Hardware Mode, but no indication of short circuit is available in Hardware Mode.
2.4.7.2
The DPM monitors the line driver output signal for valid signaling activity. The output signal is monitored for pulse
level, invalid AMI coding, pulse density, and stuck signals. In Host Mode, a DPM fault condition sets the TLOS bit in
the Alarm Status register [ALARM; addr n5] and in the Interrupt Status Register [ISR; addr n6]. In Hardware Mode,
the four internal DPM status indicators are combined (logical NOR) and output on the IRQ pin.
2.5
Three per-channel loopbacks are provided for system diagnostic testing: Local Analog Loopback, Local Digital
Loopback, and Remote Line Loopback. Loopbacks can be controlled by either hardware pins or internal register
bits. For hardware control, two dedicated pins— LLOOP and RLOOP —are provided. If configured in Host Mode,
register bits are provided for loopback control. In addition, the LLOOP and RLOOP pins can be enabled by register
bits so that loopbacks can be controlled by the hardware pins even in Host Mode. Loopback controls are detailed in
Table
Table 2-9.
29380-DSH-001-B
In Hardware Mode, the transmitter outputs are disabled while RESET is held active (low). When RESET is
2-9. Refer also to register LIU_CTL [addr n3] in
LLOOP
1
1
0
0
Loopback Control Pins
Output Disable
Transmitter Output Monitoring
Short Circuit Detect
Driver Performance Monitor
Loopbacks
Preliminary Information / Mindspeed Proprietary and Confidential
RLOOP
1
0
1
0
Mindspeed Technologies
None
Remote Line Loop
Local Analog Loop
Local Digital Loop
Chapter
3.
®
Loopback
Circuit Description
27