cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 13

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

Table 1-1.
29380-DSH-001-B
RPOSO[1:4]
RDATO[1:4]
RNEGO[1:4]
BPV[1:4]
RCKO[1:4]
RTIP[1:4]
RRING[1:4]
TPOSI[1:4]
TDATI[1:4]
TNEGI[1:4]
TCLK[1:4]
TACKI
EACKI
XOE[1:4]
TAIS[1:4]
Pin Label
Hardware Signal Definitions (1 of 5)
RX Positive Rail
(Bipolar Mode)
RX Data (Unipolar
Mode)
RX Negative Rail
(Bipolar Mode)
Bipolar Violation
(Unipolar Mode)
RX Clock Output
Receive Tip
Receive Ring
Tx Positive Rail
(Bipolar Mode)
Tx Data (Unipolar
Mode)
Tx Negative Rail
Input
TX Clock Input
T1 AIS Clock
E1 AIS Clock
Transmit Output
Enable
Transmit AIS Alarm
Signal Name
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
I/O
I/O
O
O
O
I
I
I
I
I
I
I
P
P
Transmitter (continued)
Line rate data output on the rising or falling edge of RCKO. The clock edge is
determined by the CLK_POL pin in Hardware Mode or the CLK_POL register bit
[RLIU_CR; addr n1] in Host Mode. In bipolar mode, a high signal indicates receipt
of a positive AMI pulse on RTIP/RRING inputs. In unipolar mode, RPOSO is
redefined as RDATO and a high signal indicates either a positive or negative AMI
pulse on RTIP/RRING inputs. During device reset, RPOSO/RDATO is three-stated
in host mode, and also three-stated when PD = 1 .
Line rate data output on rising or falling edge of RCKO. The clock edge is
determined by the CLK_POL pin in Hardware Mode or the CLK_POL register bit
[RLIU_CR; addr n1] in Host Mode. In bipolar mode, a high signal indicates receipt
of a negative AMI pulse on RTIP/RRING inputs. In unipolar mode, RNEGO is
redefined as BPV, and a high signal indicates the reception of a BPV which is not
part of a ZCS code (B8ZS or HDB3) if RZCS decorder is enabled. During device
reset, RNEGO/BPV is three-stated in host mode, and also three-stated when PD =
1.
Receive clock output. RCKO is the RPLL recovered line rate clock or jitter
attenuated clock output, based on the programmed jitter attenuator selection.
During device reset, RCKO is three-stated in host mode, and also three-stated
when PD = 1.
Differential AMI data inputs for direct connection to receive transformer.
Positive rail, line rate data source for transmitted XTIP/XRING output pulses. Data
is sampled on the falling edge of TCLK. In bipolar mode, a high on TPOSI causes a
positive output pulse on XTIP/XRING; and a high on TNEGI causes a negative
output pulse. In unipolar mode, TPOSI is redefined as TDATI and accepts single-
rail NRZ data. TNEGI is not used in unipolar mode.
Negative rail, line rate data input on TCLK falling edge. See TPOSI signal definition.
Transmit line rate clock. TCLK is the transmit clock for TPOSI and TNEGI data
inputs and for transmitter timing. Normally, TCLK is an input
[GCR; addr 01] and samples TPOSI/TNEGI on the falling edge. In Host Mode,
TCLK can be configured as an output to supply a line rate transmit clock from the
CLAD.
Alternate T1 and E1 transmit clock used to transmit AIS (all 1s alarm signal) when
the primary transmit clock source, TCLK, fails. TACKI (T1) or EACKI (E1) is either
manually or automatically switched to replace TCLK [LIU_CTL; addr n3]. Systems
without an AIS clock should connect TACKI and EACKI to ground.
A low signal enables XTIP and XRING output drivers. Otherwise outputs are high
impedance.
In Hardware Mode, a low signal causes AIS (unframed all 1s) transmission on
XTIP/XRING outputs. In Host Mode, these pins can be enabled or disabled
[LIU_CTL; addr n3]. If disabled, they are not used and may be left unconnected.
Transmitter
Receiver
®
Definition
Pin Descriptions
5