tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 57

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Signal Name
SYSCLK
ACE*
CE[7:0]*
OE*
SWE*
BWE[3:0]*
/BE[3:0]*
ACK*/ READY Input/output
3.1.3
External Interface Signals
Output
Output
Output
Output
Output
Output
Type
PU
System Clock
Clock for external I/O devices.
Outputs a clock in full speed mode (at the same frequency as the G-Bus clock
(GBUSCLK) frequency), half speed mode (at one half the GBUSCLK frequency), third
speed mode (at one third the GBUSCLK frequency), or quarter speed mode (at one
quarter the GBUSCLK frequency). The boot configuration signals on the ADDR[14:13]
pins select which speed mode will be used.
When this clock signal is not used, the pin can be set to H using the SYSCLK Enable
bit of the configuration register (CCFG.SYSCLKEN).
Address Clock Enable
Latch enable signal for the high-order address bits of ADDR.
Chip Enable
Chip select signals for ROM, SRAM, and I/O devices (refer to Section “3.3 Pin
multiplex”).
Output Enable
Output enable signal for ROM, SRAM, and I/O devices.
Write Enable
Write enable signal for SRAM and I/O devices.
Byte Enable/Byte Write Enable
BE[3:0]* indicate a valid data position on the data bus DATA[31:0] during read and
write bus operation. In 16-bit bus mode, only BE[1:0]* are used. In 8-bit bus mode,
only BE[0]* is used.
BWE[3:0]* indicate a valid data position on the data bus DATA[31:0] during write bus
operation. In 16-bit bus mode, only BWE[1:0]* are used. In 8-bit bus mode, only
BWE[0]* is used.
The following shows the correspondence between BE[3:0]*/BWE[3:0]* and the data
bus signals.
BE[3]*/BWE[3]*:
BE[2]*/BWE[2]*:
BE[1]*/BWE[1]*:
BE[0]*/BWE[0]*:
The boot configuration signal on the DATA[5] pin and the EBCCRn.BC bit of the
external bus controller determine whether the signals are used as BE[3:0]* or
BWE[3:0]*.
Data Acknowledge/Ready
Flow control signal (refer to Section “7.3.6 Access Modes”).
Table 3.1.3 External Interface Signals
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
3-3
Description
Chapter 3 Signals
Initial State
High
High
All High
High
High
All High
High