tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 351

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

63:22
19:14
13:11
Bit
21
20
10
63
47
31
15
Reserved
9
10.4.62 PDMAC Configuration Register (PDMCFG) 0xD220
Mnemonic
NCCMPIE
14
RSTFIFO
REQDLY
EXFER
ERRIE
13
REQDLY
Reserved
Reset FIFO
Endian Transfer
Reserved
Request Delay
Time
Error Detect
Interrupt Enable
Normal Chain
Complete
Interrupt Enable
R/W
0x0
Field Name
11
Reserved
Figure 10.4.60 PDMAC Configuration Register (1/2)
ERRIE
R/W
0x0
10
Reset FIFO (Default: 0x0)
Initializes the Read pointer and Write pointer to the FIFO in the PDMAC,
and sets the FIFO hold count to “0”. Please use the software to clear this
bit when it is set.
This is a function for a diagnosis. Usually, it is not used.
1: Performs FIFO reset.
0: Does not perform FIFO reset.
Endian Transfer (Default: 0x0)
Specifies whether to perform Endian transfer. Please use the default as is.
Set up EXFER as follows according to a Endian setup of G-Bus.
1: G-Bus in Little Endian
0: G-Bus in Big Endian
Request Delay (Default: 0x0)
G-Bus transactions for DMA transfer must be performed separated at least
by the interval this field specifies.
000: Continuously try to perform G-Bus transfer.
001: 16 G-Bus clocks
010: 32 G-Bus clocks
011: 64 G-Bus clocks
100: 128 G-Bus clocks
101: 256 G-Bus clocks
110: 512 G-Bus clocks
111: 1024 G-Bus clocks
Interrupt Enable on Error (Default: 0x0)
1: PDMAC generates an error during error detection.
0: PDMAC does not generate an error during error detection.
Interrupt Enable on Chain Done (Default: 0x0)
1: PDMAC generates an interrupt when the current chain is complete.
0: PDMAC does not generate an interrupt when the current chain is
complete.
NCCMPIE
R/W
0x0
9
NTCMPIE
R/W
0x0
Reserved
Reserved
8
10-93
CHNEN
0x0
7
R
XFRACT Reserved
R/W
0x0
22
Description
6
RSTFIFO
R/W
0x0
21
5
Chapter 10 PCI Controller
EXFER
BSWAP
R/W
0x0
R/W
0x0
20
4
19
XFRSIZE
3
R/W
0x0
Reserved
2
XFRDIRC
R/W
0x0
1
CHRST
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W : Type
0x1
48
32
16
0
⎯
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Initial value