tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 110

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

ACK*/READY (Output)
ACK*/READY(Input)
ADDR [19:0]
ADDR [19:0]
7.3.6.1
7.3.6.2
DATA [31:0]
DATA [31:0]
SYSCLK
SYSCLK
OE*
OE*
CE*
CE*
Normal Mode
ACK*/Ready Dynamic mode. The ACK*/Ready signal becomes High-Z when it is in the
ACK*/Ready Static mode.
cycle. The Wait cycle count is 0 – 0x3e (becomes the external ACK mode when set to
EBCCRn.PWT: WT = 0x3f).
External ACK Mode
ACK* signal from an external device. ACK* input is internally synchronized. Refer to Section
“7.3.7.4 ACK* Input Timing” for more information regarding timing.
When in this mode, the ACK*/Ready signal becomes an ACK* output when it is in the
Wait cycles are inserted according to the EBCCRn.PWT and EBCCRn.WT value at the access
When in this mode, the ACK*/READY pin becomes ACK* input, and the cycle is ended by the
Figure 7.3.2 External ACK Mode
Figure 7.3.1 Normal Mode
EBCCRn.PWT:WT=3
7-10
Chapter 7 External Bus Controller
EBCCRn.SHWT=0
EBCCRn.SHWT=0
expresses indeterminate values
represents indeterminate values.