tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 189

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

63:36
Bits
35:0
8.4.4
63
47
31
15
Mnemonic
SADDR
⎯
DMA Source Address Register (DM0SARn, DM1SARn)
Offset Address: DMAC0 0xB008 (ch. 0) / 0xB048 (ch. 1) / 0xB088 (ch. 2) / 0xB0C8 (ch. 3)
Reserved
Source Address
Field Name
DMAC1 0xB808 (ch. 0) / 0xB848 (ch. 1) / 0xB888 (ch. 2) / 0xB8C8 (ch. 3)
Figure 8.4.4 DMA Source Address Register
Source Address (Default: Undefined)
This field sets the physical address of the transfer source during Dual
Address transfer. This field sets the physical address of memory access
during Single Address transfer. This field is used for either Memory-to-I/O
or I/O-to-Memory transfers.
Refer to “8.3.7.1 Channel Register Settings During Single Address
Transfer” and “8.3.8.1 Channel Register Settings During Dual Address
Transfer” for more information.
During Burst transfer, the value changes once for each bus operation only
by the size that was transferred. During Single transfer, the value only
changes by the value specified by the DMA Source Address Increment
Register (DMSAIRn).
Reserved
SADDR[31:16]
SADDR[15:0]
Reserved
8-33
R/W
R/W
⎯
⎯
Description
Chapter 8 DMA Controller
36
35
SADDR[35:32]
R/W
⎯
Read/Write
R/W
48
32
16
0
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value