tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 376

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Bit
5:0
Mnemonic
STIE
Status Change
Interrupt Enable
Field Name
Figure 11.4.2 DMA/Interrupt Control Register (2/2)
Status Change Interrupt Enable (Default: 0x00)
This field sets the set conditions of the Status Change bit (STIS) of the
DMA/Interrupt Status Register (SIDISR). The condition is selected
depending on which bit of the Status Change Interrupt Status Register
(SISCISR) is set. (Multiple selections are possible.)
An SIO interrupt is asserted when STIC is “1”.
000000: Do not detect status changes.
1*****: Set “1” to STIS when the Overrun bit (OERS) is “1”.
*1****: Set “1” to STIS when a change occurs in a condition set by the
**1***: Set “1” to STIS when the Break bit (RBRKD) becomes “1”.
***1**: Set “1” to STIS when the Transmit Data Empty bit (TRDY)
****1*: Set “1” to STIS when the Transmission Complete bit (TXALS)
*****1: Set “1” to STIS when the Break Detection bit (UBRKD) becomes
CTSS Active Condition field (CTSAC) in the CTS Status bit
(CTSS).
becomes “1”.
becomes “1”.
“1”.
11-16
Description
Chapter 11 Serial I/O Port
Read/Write
R/W