tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 312

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

31:8
Bit
31
15
7
6
5
4
3
2
1
0
10.4.27 PCI Bus Arbiter Broken Master Register (PBABM)
Mnemonic
BM_W
BM_C
BM_D
BM_A
BM_B
BM_X
BM_Y
BM_Z
the PCI Master device that was acknowledged as the Broken Master when the Broken Master Check
Enable bit (BMCEN) in the PCI Bus Arbiter Configuration Register (PBACFG) is set.
the arbitration scheme when “1” is written to the corresponding BM bit.
when the PCI Bus Arbiter Request Port Register (PBAREQPORT) is changed.
This register indicates the acknowledged Broken Master. This register sets the bit that corresponds to
Regardless of the value of the Broken Master Check Enable bit, a PCI Master device is removed from
This register must be cleared to “0” since bit mapping changes, making this register value invalid
This register is only valid when using the on-chip PCI Bus Arbiter.
Reserved
Broken Master
Broken Master
Broken Master
Broken Master
Broken Master
Broken Master
Broken Master
Broken Master
Field Name
Reserved
Figure 10.4.25 PCI Bus Arbiter Broken Master Register
Broken Master A (Default: 0)
Indicates whether PCI Bus Master A is a Broken Master.
1: PCI Bus Master A was acknowledged as a Broken Master.
0: PCI Bus Master A was not acknowledged as a Broken Master.
Broken Master B (Default: 0)
Indicates whether PCI Bus Master B is a Broken Master.
1: PCI Bus Master B was acknowledged as a Broken Master.
0: PCI Bus Master B was not acknowledged as a Broken Master.
Broken Master C (Default: 0)
Indicates whether PCI Bus Master C is a Broken Master.
1: PCI Bus Master C was acknowledged as a Broken Master.
0: PCI Bus Master C was not acknowledged as a Broken Master.
Broken Master D (Default: 0)
Indicates whether PCI Bus Master D is a Broken Master.
1: PCI Bus Master D was acknowledged as a Broken Master.
0: PCI Bus Master D was not acknowledged as a Broken Master.
Broken Master W (Default: 0)
Indicates whether PCI Bus Master W is a Broken Master.
1: PCI Bus Master W was acknowledged as a Broken Master.
0: PCI Bus Master W was not acknowledged as a Broken Master.
Broken Master X (Default: 0)
Indicates whether PCI Bus Master X is a Broken Master.
1: PCI Bus Master X was acknowledged as a Broken Master.
0: PCI Bus Master X was not acknowledged as a Broken Master.
Broken Master Y (Default: 0)
Indicates whether PCI Bus Master Y is a Broken Master.
1: PCI Bus Master Y was acknowledged as a Broken Master.
0: PCI Bus Master Y was not acknowledged as a Broken Master.
Broken Master Z (Default: 0)
Indicates whether PCI Bus Master Z is a Broken Master.
1: PCI Bus Master Z was acknowledged as a Broken Master.
0: PCI Bus Master Z was not acknowledged as a Broken Master.
Reserved
8
10-54
BM_A BM_B BM_C BM_D BM_W BM_X BM_Y BM_Z
7
6
Description
5
Chapter 10 PCI Controller
4
0xD110
0x00
R/W
3
2
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16
0
⎯
: Type
: Initial value
: Type
: Initial value