tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 375

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

31:16
10:9
Bit
8:6
15
14
13
12
11
TDE
R/W
31
15
0
11.4.2
RDE
R/W
Mnemonic
14
0
CTSAC
SPIE
RDE
TDE
RIE
TIE
R/W
TIE
DMA/Interrupt Control Register 0 (SIDICR0)
DMA/Interrupt Control Register 1 (SIDICR1)
13
0
These registers use either DMA or interrupts to execute the Host Interface.
R/W
RIE
12
Reserved
Transmit DMA
Transfer Enable
Receive DMA
Transfer Enable
Transmit Data
Empty Interrupt
Enable
Reception Data
Full Interrupt
Enable
Reception Error
Interrupt Enable
CTSS Active
Condition
Reserved
0
Field Name
SPIE
R/W
11
0
Figure 11.4.2 DMA/Interrupt Control Register (1/2)
10
CTSAC
R/W
00
Transmit DMA Enable (Default: 0)
This field sets whether to use DMA in the method for writing transmission
data to the Transmit FIFO.
0: Do not use DMA.
1: Use DMA.
Receive DMA Enable (Default: 0)
This field sets whether to use DMA in the method for reading reception
data from the Receive FIFO.
0: Do not use DMA.
1: Use DMA.
Transmit Data Empty Interrupt Enable (Default: 0)
When there is open space in the Transmit FIFO, this field sets whether to
signal an interrupt. Set “0” when in the DMA Transmit mode (TDE = 1).
0: Do not signal an interrupt when there is open space in the Transmit
1: Signal an interrupt when there is open space in the Transmit FIFO.
Receive Data Full Interrupt Enable (Default: 0)
This field sets whether to signal interrupts when reception data is full
(SIDISRn.RDIS = 1) or a reception time out (SIDISRn.TOUT = 1) occurs.
Set to “0” when in the DMA Receive mode (RDE = 1).
0: Do not signal interrupts when reception data is full/reception time out
1: Signal interrupts when reception data is full/reception time out occurred.
Receive Data Error Interrupt Enable (Default: 0)
This field sets whether to signal interrupts when a reception error (Frame
Error, Parity Error, Overrun Error) occurs (SIDISR.ERI = 1).
0: Do not signal reception error interrupts.
1: Signal reception error interrupts.
CTSS Active Condition (Default: 00)
This field specifies status change interrupt request conditions using the
CTS Status (CTSS) of the Status Change Interrupt Status Register.
00: Do not detect CTS signal changes.
01: Rising edge of the CTS pin
10: Falling edge of the CTS pin
11: Both edges of the CTS pin
FIFO.
occurred.
9
Reserved
8
Reserved
11-15
6
Description
5
0xF304 (Ch. 0)
0xF404 (Ch. 1)
Chapter 11 Serial I/O Port
000000
STIE
R/W
16
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
: Type
: Initial value
: Type
: Initial value
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