tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 221

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Row address width = 11
Column address width = 8
Row Address Width = 11
Column Address Width = 9
Address bit
ADDR [19:5]
Column
Address
Row Address
Address Bit
ADDR [19:5]
Column
Address
Row Address
Row Address Width = 11
Column Address Width = 10
Address Bit
ADDR [19:5]
Column
Address
Row Address
Row Address Width = 12
Column Address Width = 8
Address Bit
ADDR [19:5]
Column
Address
Row Address
Row Address Width = 12
Column Address Width = 9
Address Bit
ADDR [19:5]
Column
Address
Row Address
Row Address Width = 12
Column Address Width = 10
Address Bit
ADDR [19:5]
Column
Address
Row Address
9.3.2.2
(B0)
(B0)
(B0)
(B0)
(B0)
(B0)
Address Signal Mapping (64-bit Data Bus)
bank selection in memory with a two-bank configuration. [B1:B0] are used in the bank selection
in memory with a four-bank configuration. Bits with the description "L/H" output High when
performing auto-precharging, or output Low when not performing auto-precharging.
19
22
22
19
23
23
19
24
24
19
23
23
19
24
24
19
25
25
Table 9.3.2 shows the address signal mapping when using a 64-bit data bus. B0 is used in the
Table 9.3.2 Address Signal Mapping (64-bit Data Bus) (1/2)
(B1)
(B1)
(B1)
(B1)
(B1)
(B1)
18
23
23
18
23
23
18
23
23
18
24
24
18
25
25
18
26
26
17
21
21
17
23
23
17
23
23
17
23
23
17
24
24
17
25
25
16
20
20
16
23
23
16
24
24
16
22
22
16
22
22
16
22
22
(AP)
(AP)
(AP)
(AP)
(AP)
(AP)
L/H
L/H
L/H
L/H
L/H
L/H
15
21
15
21
15
21
15
21
15
21
15
21
L/H
14
20
14
23
20
14
23
20
14
24
20
14
24
20
14
24
20
9-5
L/H
13
19
13
22
19
13
22
19
13
23
19
13
23
19
13
23
19
12
10
18
12
10
18
12
10
18
12
10
18
12
10
18
12
10
18
Chapter 9 SDRAM Controller
11
17
11
17
11
17
11
17
11
17
11
17
9
9
9
9
9
9
10
16
10
16
10
16
10
16
10
16
10
16
8
8
8
8
8
8
15
15
15
15
15
15
9
7
9
7
9
7
9
7
9
7
9
7
14
14
14
14
14
14
8
6
8
6
8
6
8
6
8
6
8
6
13
13
13
13
13
13
7
5
7
5
7
5
7
5
7
5
7
5
12
12
12
12
12
12
6
4
6
4
6
4
6
4
6
4
6
4
11
11
11
11
11
11
5
3
5
3
5
3
5
3
5
3
5
3