tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 338
tmpr4937
Manufacturer Part Number
tmpr4937
Description
64-bit Tx System Risc
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMPR4937.pdf
(552 pages)
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63:39
35:8
Bit
7:1
38
37
36
63
47
31
15
10.4.49 P2G I/O Space G-Bus Base Address Register (P2GIOGBASE)
Mnemonic
P2GIOEN
BA[35:8]
BSWAP
EXFER
Reserved
I/O Space Enable Target I/O Space Enable (Default: 0x0) Controls whether the I/O Space for
Byte Swap
Endian Transfer
Memory Space
Base Address 2
Reserved
Field Name
BA[15:8]
0x00
R/W
Figure 10.4.47 P2G I/O Space G-Bus Base Address Register
Reserved
target access is valid or invalid.
When this bit is set to invalid, Writes to the I/O Space Base Address
Register of the PCI Configuration Register become invalid. Also, “0” is
returned to Reads as a response.
1: Validates I/O Space for target access.
0: Invalidates I/O Space for target access.
Byte Swap Disable
(Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte
swapping of the I/O Space for target access.
1: Do not perform byte swapping.
0: Perform byte swapping.
Please use the default state in most situations. If this bit is changed to “1”
when in the Big Endian Mode, the byte order of transfer to the I/O Space
through DWORD (32-bit) access will not change.
Endian Transfer
(Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian
Transfer of the I/O Space for target access.
1: Performs Endian Transfer.
0: Does not perform Endian Transfer.
Please use the default state.
Base Address 2 (Default: 0x000)
Sets the G-Bus base bus address of the I/O Space for target access. Can
set the base address in 256-byte units.
BA[31:16]
Reserved
8
0x0000
R/W
10-80
39
7
P2GIOEN
R/W
0x0
38
Description
BSWAP
0x0/0x1 0x1/0x0
R/W
37
Chapter 10 PCI Controller
EXFER
R/W
36
Reserved
35
BA[35:32]
R/W
0x0
0xD198
Read/Write
R/W
R/W
R/W
R/W
48
32
16
0
⎯
⎯
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
: Type
: Initial value
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