tmpr4937 TOSHIBA Semiconductor CORPORATION, tmpr4937 Datasheet - Page 146

• Manufacturer Part Number: tmpr4937
• Description: 64-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

OE*/BUSSPRT*
7.5.9
OE*/BUSSPRT*
ADDR[19:0]
DATA[31:0]
SYSCLK
ADDR[19:0]
DATA[31:0]
SWE*
BWE*
ACE*
ACK*
SYSCLK
CE*
BE*
Figure 7.5.23 1-word Single Write (0 Wait, SHWT=0, External ACK*, 32-bit Bus)
Figure 7.5.24 1-word Single Read (0 Wait, SHWT=0, External ACK*, 32-bit Bus)
External ACK Mode Access (32-bit Bus)
SWE*
BWE*
ACE*
ACK*
CE*
BE*
Note 1: The TX4937 sets the ACK* signal to High Impedance in the S1 State.
Note 2: External devices drive the ACK* signal to Low (assert the signal) by the ES1 State.
Note 3: External devices drive the ACK* signal to High (deassert the signal) in the ES2
f
State. If an external device is late in asserting ACK*, then the Wait State is inserted
for the amount of time the external device is late. If a certain condition is met, it is
okay for the ACK* signal to be driven to Low for 1 clock cycle or more. See 7.3.7.4
ACK* Input Timing (External ACK Mode) for more information.
f
f
S1
S1
ES1
ES1
7-46
ES2
ES2
Chapter 7 External Bus Controller
f
0
0
0
ES3
S2
S2
S3
S3
f
f
f