zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 87

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

PLL0/1/2/3 (PLL CONTROL 0/1/2/3 REGISTER, 0x2286, 0x2287, 0x2288, 0x228B) R/W.
To modify the PLL offset frequency, refer to Table 47 below.
As shown in Table 47, the delta K correction factor is determined based on the values in the
FRAC_K [19:0] registers as follows.
*1LSB = 195.31Hz
* The values of PLL0, PLL1, PLL2 [3:0] in Table 47 are HEX.
When using a 16MHz crystal, the values of PLL0, PLL1 and PLL2 need to be adjusted in order
to define the adjustment to the channel frequency as shown in Table 47.
New Frequency = Original Frequency + Frequency Offset. Here, delta K, which is the
Frequency Offset, can be derived from the following formula.
The New Frequency can be obtained by converting the delta K calculated above to Hex format
and adding it to the value of the registers for the current frequency.
In order to adjust the frequency of channel 26, set PLL3 (0x228B) to 0x32 and then adjust it.
PLL4 (PLL CONTROL 4 REGISTER, 0x2289)
This register is used to process an automatic frequency calibration (AFC) when changing the locking
frequency of the PLL.
PLL5 (PLL CONTROL 5 REGISTER, 0x228A)
This register is used to check whether PLL is locked or not.
To change the channel setting, the PLL0, PLL1, PLL2, PLL3, PLL4 registers need to be
changed by the following procedure:
Bit
5:0
5:0
7
6
7
6
Rev A
Offset Frequency
1) Change the RF RX-path to the power-down state by setting the RXRFPD register to
AFCEN
PLLOC
AFCST
Name
ART
00000000.
K
*195.31Hz
100kHz
10kHz
1MHz
Register Name
1kHz
Automatic Frequency Calibration Start. Used to request the start of
AFC. AFC is processed when the AFCSTART is set to ‘1’. After the
AFC process, the AFCSTART field is automatically cleared to ‘0’.
Automatic Frequency Calibration Enable. Used to enable the AFC
process and should be set to ‘1’ to run AFC.
Reserved
Reserved
Shows the locking status of PLL circuit. When this field is set to ‘1’, the
PLL circuit is locked. When ‘0’, the PLL circuit is not locked.
Reserved
Table 48 – Phase Lock Loop Control Registers
delta K = Frequency Offset / 195.31Hz
Table 47 – FRAC_K[19:0] Registers
Address: 0x2286
FRAC_K [19:12]
Document No. 0005-05-07-00-000
PLL0
01
00
00
00
00
ZIC2410 Datasheet
Descriptions
Address: 0x2287
FRAC_K [11:4]
PLL1
40
20
03
00
00
Address: 0x2288
FRAC_K [3:0]
PLL2 [3:0]
0
0
3
5
1
R/W
R/W
R/W
R/W
R/W
Page 87 of 119
111111
111111
Reset
Value
0
0
0
0