zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 61

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

MTFCPUSH (TX FIFO PUSH DATA REGISTER, 0x2000)
MTFCWP (TX FIFO WRITE POINTER REGISTER, 0x2001)
MTFCRP (TX FIFO READ POINTER REGISTER, 0x2002)
MTFCCTL (TX FIFO CONTROL REGISTER, 0x2003)
MTFCSTS (TX FIFO STATUS REGISTER, 0x2004)
MTFCSIZE (TX FIFO Data Size Register, 0x2005)
MTFCSBASE (TX FIFO AES ENCRYPTION DATA START POINTER REGISTER, 0x2007)
MTFCSLEN (TX FIFO AES ENCRYPTION DATA LENGTH REGISTER, 0x2008)
7:0
7:0
7:0
7:3
5:2
7:0
7:0
7:0
Bit
2
1
0
7
6
1
0
Rev A
MTFCRP8
MTFCSIZE
MTFCWP
MTFCWP
MTFCSBA
MTFCSLE
MTFCPU
MTFCRP
EMPTY
Name
FULL
ASA
ENA
CLR
SH
SE
N
8
When data is written to this register, it is stored in TX FIFO. The
size of TX FIFO is 256 byte and it can be accessed by MCU or
VTXDMA.
TX FIFO Write Pointer: Total is 9-bit with MTFCWP8 in
MTFCSTS register. It is increased by ’1’ whenever writing data to
TX FIFO.
TX FIFO Read Pointer: Total is 9-bit with MTFCRP8 in MTFCSTS
register. It is increased by ‘1’ whenever reading data from TX FIFO.
Reserved
When this field is set to ‘1’, it automatically sets the starting address
of the packet and the length of the packet encrypted by the AES
engine to the information of the packet which is to be transmitted.
When this field is set to ‘1’, MTXFIFO is enabled.
When this field is set to ‘1’, MTFCWP, MTFCRP, MTFCSTS,
MTFCSIZE, MTFCRM registers are initialized.
Total is 9-bit address with MTFCWP register. This field is the MSB
and is used to detect wrap around of a circular FIFO.
Total is 9-bit address with MTFCRP register. This field is the MSB
and is used to detect wrap around of a circular FIFO.
Reserved
Set to ‘1’ when data size in the TX FIFO is 256 byte.
Set to ‘1’ when data size in the TX FIFO is ‘0’.
Represents the number of valid data bytes in theTX FIFO. This
field value is valid when FIFO status is normal and is calculated by
the difference between MTFCWP (0x2001) and MTFCRP (0x2002).
Represents the starting address of data to be encrypted by the AES
engine in the TX FIFO. This field is set by the MCU or is set
automatically to the starting address of a packet to be transmitted
when the ASA field in the MTFCCTL register is set to ‘1’.
Represents the length of the data to be encrypted by the AES
engine in the TX FIFO. This field is set by the MCU or is set
automatically to the length of a packet to be transmitted when the
ASA field in the MTFCCTL register is set to ‘1’.
Table 34 – MAC TX FIFO Registers
Document No. 0005-05-07-00-000
ZIC2410 Datasheet
Descriptions
R/W
W/O
R/W
R/W
R/W
R/W
R/W
R/W
R/O
R/O
RW
R/O
Page 61 of 119
RW
RW
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
1
1
0
0
0
0
0
0