zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 62

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

Table 35 describes the registers for controlling MAC RX FIFO.
MRFCPOP (RX FIFO POP Data Register, 0x2080)
MRFCWP (RX FIFO WRITER POINTER REGISTER, 0x2081)
MRFCRP (RX FIFO READ POINTER REGISTER, 0x2082)
MRFCCTL (RX FIFO CONTROL REGISTER, 0x2083)
MRFCSTS (RX FIFO STATUS REGISTER, 0x2084)
MRFCSIZE (RX FIFO Data Size Register, 0x2085)
MRFCSBASE (RX FIFO AES DECRYPTION DATA START POINTER REGISTER, 0x2087)
MRFCSLEN (RX FIFO AES DECRYPTION DATA LENGTH REGISTER, 0x2088)
7:0
7:0
7:0
7:3
5:2
7:0
7:0
7:0
Bit
2
1
0
7
6
1
0
Rev A
MRFCSIZE
MRFCPOP
MRFCWP
MRFCWP8
MRFCSBA
MRFCRP8
MRFCSLE
MRFCRP
EMPTY
Name
FULL
ASA
ENA
CLR
SE
N
This register can read data in RX FIFO. The size of RX FIFO is
256 byte and it can be accessed by the MCU or by VRXDMA.
RX FIFO Write Pointer: Total is 9-bit with MRFCWP8 in the
MRFCSTS register. It is increased by ’1’ whenever data is written
to the RX FIFO.
RX FIFO Read Pointer: Total is 9-bit with MRFCRP8 in the
MRFCSTS register. It is increased by ‘1’ whenever data is read
from the RX FIFO.
Reserved
When this field is set to ‘1’, it automatically sets the starting address
of a packet and the length of a packet decrypted by the AES engine
to the information of the received packet.
When this field is set to ‘1’, MRXFIFO is enabled.
When this field is set to ‘1’, MRFCWP, MRFCRP, MRFCSTS,
MRFCSIZE, MRFCRM registers are initialized.
Total is 9-bit address with MRFCWP register. This field is the MSB,
and is used to detect wrap around of a circular FIFO.
Total is 9-bit address with MRFCRP register. This field is the MSB,
and is used to detect wrap around of a circular FIFO.
Reserved
Set to ‘1’ when data size in the RX FIFO is 256 byte.
Set to ‘1’ when data size in the RX FIFO is ‘0’.
Represents the number of valid data bytes in the RX FIFO. This
field value is valid when the FIFO status is normal and is calculated
by the difference between MRFCWP and MRFCRP.
Represents the starting address of the data to be decrypted by the
AES engine in the RX FIFO. This field is set by the MCU or is set
automatically to the starting address of the received packet when
the ASA field in the MRFCCTL register is set to ‘1’.
Represents the length of the data to be decrypted by the AES
engine in the RX FIFO. This field is set by the MCU or is set
automatically to the length of the received packet when the ASA
field in the MRFCCTL register is set to ‘1’.
Table 35 – MAC RX FIFO Registers
Document No. 0005-05-07-00-000
ZIC2410 Datasheet
Descriptions
R/W
W/O
R/W
R/W
R/W
R/W
R/W
R/W
R/O
RW
R/O
R/O
Page 62 of 119
RW
RW
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
1
1
0
0
0
0
0
0