zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 24

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

The following table describes the status of voltage regulator, oscillator, and sleep timer in
normal mode (PM0) and each Power-Down mode.
When exiting from a Power-Down mode initiated by a Sleep Timer interrupt, RTDLY (0x22F4)
register specifies the delay time for oscillator stabilization. If the delay time is too short, the
oscillator can become unstable and cause a problem of fetching a wrong instruction command
in the MCU.
In addition, there are two Power-Down modes that can be only used in the MCU. One is PD
(Power-Down) mode and the other is IDLE mode. PD (Power-Down) mode of MCU is enabled
by setting PD in PCON register to ‘1’. In PD (Power-Down) mode, all the clocks of MCU are
stopped and current consumption is minimized. When interrupt, which is allowed for wake-up,
occurs, it exits from PD mode. After exiting, first, the corresponding interrupt service routine is
executed. And then, the next instruction after the instruction for setting PD to ‘1’ is executed.
In IDLE mode, clocks of all the blocks in the MCU except the peripherals are stopped. The
current consumption is 2.7mA. When an interrupt occurs (except a timer interrupt or an external
interrupt) the IDLE bit is cleared and the device exits from the IDLE mode. The required
interrupt service routine is then executed and the next instruction (after the instruction setting
IDLE to ‘1’) is executed.
Power Mode
Rev A
③ External interrupt Wake Up
PM0
PM1
PM2
PM3
The following shows the time of External Interrupt Wake Up. The time, until system is
operated, is different based on the releasing time of external interrupt. For example,
external interrupt can be released before RTDLY minimum time or after RTDLY
minimum time. By considering these two causes, it is recommended to set RTDLY to
over 600μsec at least. In addition, Register RTDLY should be set over ’0x11’ at least to
stabilize crystal.
AVREG
Figure 10 – External Timer Interrupt: Wake Up Times
OFF
OFF
OFF
ON
Table 9 – Status in Power-Down Modes
Document No. 0005-05-07-00-000
ZIC2410 Datasheet
DVREG
OFF
OFF
ON
ON
Main OSC
OFF
OFF
OFF
ON
Based on the CEL' reference circuit.
Sleep Timer
OFF
ON
ON
ON
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