zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 36

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

There are more registers such as the Modem Control Register, the Line Status Register, the
Modem Status Register and the Port Enable Register in the UART0 block. This document
doesn’t include these registers because they are not commonly used. For more detailed
information on their use, please contact CEL.
The following registers are to control UART1.
RBR (UART1 RECEIVE BUFFER REGISTER, 0x2510)
THR (UART1 TRANSMITTER HOLDING REGISTER, 0x2510)
DLL (UART1 DIVISOR LSB REGISTER, 0x2510)
Note: After the data is written to the DLM register, it should be written in this register. When the data is
written to DLL register, the clock divisor begins. Baud rate is calculated by the following equation.
IER (UART1 INTERRUPT ENABLE REGISTER, 0x2511)
DLM (UART1 DIVISOR LATCH MSB REGISTER, 0x2511)
IIR (UART1 INTERRUPT IDENTIFICATION REGISTER, 0x2512)
Note: IIR register uses the same address as FCR register in Table 22 below. IIR register is read-only
and FCR register is write-only.
Bit
1:0
Bit
7:0
7:0
7:0
7:4
7:0
7:4
3:1
2
3
2
1
0
0
Rev A
Baud rate = clock_speed / (7 × divisor_latch_value)
PENDING
EDSSI
ETBEI
ERBEI
Name
Name
INTID
WLS
RBR
ELSI
DLM
THR
STB
DLL
Number of Stop Bits. When this field is set to ‘1’, 2 stop bit is
used. When transmitting a word (character) of 5 bit length, 1.5 stop
bit is used. When this field is ‘0’, 1 stop bit is used.
Word Length Select.
Read the received data
This register stores the data to be transmitted. The address is the
same as the RBR register. When accessing this address, received
data (RBR) is read and the data to be transmitted is stored.
This register can be accessed only when the DLAB bit in the LCR
register is set to ‘1’. This register shares a 16-bit register with the
DLM register (below) occupying the lower 8 bits. This full 16-bit
register is used to divide the clock.
Reserved
Enable MODEM Status Interrupt.
When this field is set to ‘1’, Modem status interrupt is enabled.
Enable Receiver Line Status Interrupt.
Enable Transmitter Holding Register Empty Interrupt
Enable Received Data Available Interrupt
This register can be accessed only when the DLAB bit in the LCR
register is set to ‘1’. This register shares a 16-bit register with the
DLL register (above) occupying the higher 8 bits. This full 16-bit
register is used to divide the clock.
Reserved
Interrupt Identification. Refer to the Table 21.
Shows whether the interrupt is pending or not. When this field is ‘0’,
the interrupt is pending.
0: 5bit Word
1: 6bit Word
2: 7bit Word
3: 8bit Word
Table 21 – UART1 Interrupt Lists
Document No. 0005-05-07-00-000
Table 20 – UART1 Registers
ZIC2410 Datasheet
Descriptions
Descriptions
R/W
R/W
R/W
R/W
W/O
R/W
R/W
R/W
R/W
R/W
R/W
R/O
R/O
R/O
R/O
Page 36 of 119
Reset
Reset
Value
Value
0x00
0x00
0x00
0x00
0
3
0
0
0
0
0
0
0
1