zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 59

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

ZIC2410 Datasheet
Figure 30 – IEEE 802.15.4 Frame Format
Synchronization Header (SHR)
In IEEE802.15.4 standard, a frame format includes the synchronization header (SHR) for the
purpose of adjusting the gain of the receiving signal, detecting packet and obtaining
synchronization.
SHR is consisted of a preamble and Start of Frame Delimiter (SFD). The Preamble is formatted
by repeating the same 8 symbols (‘0’) in 4 bytes. 1 byte SFD is used to detect the frame start
and obtain timing synchronization and it is defined as 0XA7 in IEEE802.15.4 standard.
PHY Header (PHR)
The Length field is used to define the size of the MPDU or the PSDU.
The value clarified in length field doesn’t include the length field itself. However, the length of
Frame Check Sequence (FCS) is included. The PHY block takes data up to the size defined by
the length field in TX FIFO, and transmits that data.
MAC Header (MHR)
This field is consisted of frame control field (FCF), data sequence number (DSN) and address
information. FCF includes the frame information such as frame type or addressing mode and so
on. DSN means the sequence of packet. In other words, DSN is incremented after
transmitting. Therefore, next packet has a different DSN. For detailed information, refer to the
IEEE802.15.4 standard.
MAC Footer (MFR)
This field is called as frame check sequence (FCS) and it follows the last data of MAC payload
byte. FCS polynomial is as follows.
x16 + x12 + x5 + 1
1.8.1 RECEIVED MODE
When receiving the data from the PHY block, the MAC block stores the data in the RX FIFO.
The data in the RX FIFO can be decrypted by the PCMD1 (0X2201) register or it can be read by
the MRFCPOP (0x2080) register. Data decryption is implemented by the AES-128 algorithm,
which supports CCM* mode by ZigBee and CTR/CBC-MAC/CCM mode by IEEE 802.15.4. The
RX Controller controls the process described above. When decrypting the data, the received
frame data length is modified and the modified value is stored in the LSB of each frame by the
hardware again.
The size of the RX FIFO is 256 bytes and it is implemented by a Circular FIFO with a Write
Pointer and a Read Pointer. The RX FIFO can store several frame data received from the PHY
block. Since the LSB of each frame data represents the frame data length, it can be accessed
by the Write pointer and the Read Pointer.
Rev A
Document No. 0005-05-07-00-000
Page 59 of 119