zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 21

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

IE (INTERRUPT ENABLE REGISTER, 0xA8)
The EA bit in the IE register is the global interrupt enable signal for all interrupts. In addition, each
interrupt is masked by each interrupt enable bit. Therefore, in order to use an interrupt, both EA and
the specific interrupt enable bit should be set to ‘1’. When the bit for each interrupt is ‘0’, that
interrupt is disabled. When the bit for each interrupt is ‘1’, that interrupt is enabled.
IP (INTERRUPT PRIORITY REGISTER, 0xB8)
If a bit corresponding to each interrupt is ‘0’, the corresponding interrupt has lower priority and if a bit
is ‘1’, the corresponding interrupt has higher priority.
EIE (EXTENDED INTERRUPT ENABLE REGISTER, 0xE8)
If a bit is ‘0’, corresponding interrupt is disabled and if a bit is ‘1’, corresponding interrupt is enabled.
Refer to the following table.
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
Rev A
VCEIE
RTCIE
AESIE
Name
SPIIE
T3IE
ES1
ES0
EX1
EX0
PS1
PS0
PX1
PX0
ET1
ET0
PT1
PT0
EA
Global interrupt enable
UART1 interrupt enable 1: interrupt enabled.
Reserved
UART0 interrupt enable 1: interrupt enabled.
Timer1 interrupt enable 1: interrupt enabled.
External interrupt1 enable 1: interrupt enabled.
Timer0 interrupt enable 1: interrupt enabled.
External interrupt0 enable 1: interrupt enabled.
Reserved
UART1 interrupt priority
1: UART1 interrupt has higher priority.
Reserved
UART 0 interrupt priority
1: UART0 interrupt has higher priority.
Timer1 interrupt priority
1: Timer1 interrupt has higher priority.
External interrupt1 interrupt priority
1: External interrupt1interrupt has higher priority.
Timer0 interrupt priority
1: Timer0 interrupt has higher priority.
External interrupt0 interrupt priority
1: External interrupt0 interrupt has higher priority.
Reserved
Voice Interrupt Enable.
SPI Interrupt Enable
Sleep Timer Interrupt Enable
Timer3 Interrupt Enable
AES Interrupt Enable
0: No interrupt will be acknowledged.
1: Each interrupt source is individually enabled or
disabled by setting its corresponding enable bit.
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt disabled
1: Interrupt enabled
Table 7 – INTERRUPT Registers
Document No. 0005-05-07-00-000
Descriptions
ZIC2410 Datasheet
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Page 21 of 119
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0