zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 20

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

1.5 INTERRUPT SCHEMES
The program interrupt functions of the embedded MCU are similar to other microprocessors.
When an interrupt occurs, the interrupt service routine at the corresponding vector address is
executed. When the interrupt service routine process is completed, the program is resumed
from the point of time at which the interrupt occurred. Interrupts can be initiated from the
internal operation of the embedded microprocessor (e.g. the overflow of the timer count) or from
an external signal.
The ZIC2410 has 13 interrupt sources. Table 6 describes the detailed information for each of
the interrupt sources. The ‘Interrupt Address’ indicates the address where the interrupt service
routine is located. The ‘Interrupt Flag’ is the bit that notifies the MCU that the corresponding
interrupt has occurred. ‘Interrupt Enable’ is the bit which decides whether each interrupt has
been enabled. ‘Interrupt Priority’ is the bit which decides the priority of the interrupt. The
‘Interrupt Number’ is the interrupt priority fixed by the hardware. That is, when two or more
interrupts having the same ‘Interrupt Priority’ value, occur simultaneously, the lower ‘Interrupt
Number’ is processed first.
Note 1: In the case of a UART Interrupt, bit [0] of the IIR register (0x2502, 0x2512) in the UART block is used as a
flag. Also, the Tx, Rx, Timeout, Line Status and Modem Status interrupts can be distinguished by bit [3:1] value.
For more detailed information, refer to the UART0/1 description in Section 1.7.6.
Note 2: In the case of an SPI interrupt, there is another interrupt enable bit in the SPI register besides EIE.SPIIE.
In order to enable an SPI interrupt, both SPIE in the SPCR (0x2540) register and EIE.SPIIE should be set to ‘1.
SPIF in the SPSR (0x2541) register acts as an interrupt flag.
Note 3: In case of a Voice interrupt, there are interrupt enable registers and interrupt flag registers in the voice
block. The interrupt enable register are VTFINTENA (0x2770), VRFINTENA (0x2771) and VDMINTENA (0x2772).
The interrupt flag register are VTFINTVAL (0x2776), VRFINTVAL (0x2777), and VDMINTVAL (0x2778). There are
24 interrupt sources. When both an interrupt enable signal and an interrupt flag signal are set to ‘1,’ voice interrupt
is enabled.
Interrupt
Number
Rev A
10
11
12
13
14
0
1
2
3
4
7
8
9
UART0 Interrupt (RX)
UART1 Interrupt (RX)
UART0 Interrupt (TX)
Sleep Timer Interrupt
UART1Interrupt (TX)
External Interrupt0
External Interrupt1
Timer0 Interrupt
Timer1 Interrupt
Timer2 Interrupt
Timer3 Interrupt
Interrupt Type
Voice Interrupt
PHY Interrupt
AES Interrupt
SPI Interrupt
Table 6 – Interrupt Descriptions
Document No. 0005-05-07-00-000
Interrupt
Address
000BH
001BH
003BH
004BH
005BH
0003H
0013H
0023H
0043H
0053H
0063H
0068H
0073H
ZIC2410 Datasheet
Interrupt Flag
EICON.RTCIF
EXIF.PHYIF
EXIF.AESIF
TCON.TF0
TCON.TF1
TCON.IE0
TCON.IE1
EXIF.T2IF
EXIF.T3IF
Note 1
Note 1
Note 2
Note 3
EIE.RTCIE
EIE.VCEIE
EIE.AESIE
EIE.SPIIE
EIE.RFIE
Interrupt
EIE.T2IE
EIE.T3IE
Enable
IE.EX0
IE.EX1
IE.ES0
IE.ES1
IE.ET0
IE.ET1
EIP.RTCIP
EIP.AESIP
EIP.VCEIP
EIP.SPIIP
Interrupt
EIP.RFIP
EIP.T2IP
EIP.T3IP
Priority
IP.PX0
IP.PT0
IP.PX1
IP.PT1
IP.PS0
IP.PS1
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