zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 32

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

1.7.4 SLEEP TIMER
The Sleep Timer can generate time interval such as 1 or 2 seconds with a 32.768 KHz clock
source. The Sleep Timer (ST) is used to exit from the Power-Down mode.
The clock source desired can be generated from an external crystal or the internal RC oscillator.
ST is activated as setting RTEN bit to ‘1’ and the interrupt interval can be programmed by
setting RTCON [6:0], RTINT1 and RTINT0 register.
Sleep Timer Interrupt Interval
RTCON [6:0], RTINT1 and RTINT0 register represent RTINT [22:0] (23-bit) and the timer
interval is determined by this value. If ST clock source acts as 32.786KHz, one ST cycle is
1/32768 second and the timer interval is RTINT * (1/32768) second. Therefore, ST interrupt
occurs per (RTINT * 30.5) µs and maximum is 256 second.
RTDLY (SLEEP TIMER DELAY REGISTER, 0x22F4)
This register is used when the MCU exits from a power-down state initiated by the ST interrupt.
RTDLY specifies the delay time for oscillator stabilization. When the MCU exits from power-
down mode, the MCU executes the next instruction after the delay time.
RTCON (SLEEP TIMER CONTROL REGISTER, 0x22F5)
RTINT1 (SLEEP TIMER INTERRUPT INTERVAL 1, 0x22F6)
RTINT0 (SLEEP TIMER INTERRUPT INTERVAL 0, 0x22F7)
Bit
6:0
7:0
7:0
Bit
7:0
7
Rev A
RTCSEL
RTDLY
[22:16]
RTINT
RTINT
RTINT
Name
Name
[15:8]
[7:0]
Sleep Timer Select: When this field is set to ‘1’, internal RCOSC
is used as a clock source. When this field is set to ‘0’, external
32.768KHz crystal is used as a clock source. When this field is
set to ‘0’ and external crystal is not turned on, ST does not act.
This field determines ST interrupt interval with RTINT0 and
RTINT1
This field determines the ST interrupt interval with RTINT0 and
RTCON [6:0]
This field determines ST interrupt interval with RTINT1 and
RTCON [6:0]
Delay Time = RTDLY × 4 / 32.768KHz when ST clock source is
32.768KHz. The value of RTDLY should be greater than 2.
Table 16 – Sleep Timer Delay Registers
Table 15 – Sleep Timer Registers
Document No. 0005-05-07-00-000
ZIC2410 Datasheet
Descriptions
Descriptions
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Reset
Reset
Value
Value
0x00
0x00
0x08
0x11
1