zl50075 Zarlink Semiconductor, zl50075 Datasheet - Page 7

• Manufacturer Part Number: zl50075
• Description: 32 K Channel Digital Switch With High Jitter Tolerance, Rate Conversion Per Group Of 2 Streams 8, 16, 32 Or 64 Mbps , And 64 Inputs And 64 Outputs
• Manufacturer: Zarlink Semiconductor

Change Summary
The following table captures the changes from the April 2005 issue.
The following table captures the changes from the July 2004 issue.
Page
Page
25
26
26
27
38
10
48
50
51
52
53
54
55
11
10.1.1, “Read Cycle“
Figure 9 "Read Cycle Operation"
10.1.2, “Write Cycle“
Figure 10 "Write Cycle Operation"
Table 21 “BER Counter Group and
Stream Address Mapping“
"Pin Description" - CKo0-1
"Pin Description" - DTA, WAIT
“AC Electrical Characteristics1 - FPi0
and CKi0 Timing“
(1) “AC Electrical Characteristics1 -
FPO0-1 and CKO0-1 (65.536 MHz)
Timing“
(2) “AC Electrical Characteristics1 -
FPO0-1 and CKO0-1 (32.768 MHz)
Timing“
(3) “AC Electrical Characteristics1 -
FPO0-1 and CKO0-1 (16.384 MHz)
Timing“
(4) “AC Electrical Characteristics1 -
FPO0-1 and CKO0-1 (8.192 MHz)
Timing“
“AC Electrical Characteristics - Output
Clock Jitter Generation“
“AC Electrical Characteristics1 - Serial
Data Timing2 to CKi“
Figure 14 "Serial Data Timing to CKi"
“AC Electrical Characteristics - Serial
Data Timing1 to CKo2“
Figure 15 "Serial Data Timing to CKo"
Item
Item
Zarlink Semiconductor Inc.
ZL50075
Clarified WAIT signal description in Read Cycle.
Corrected WAIT signal tristate timing in Read Cycle.
Clarified WAIT signal description in Write Cycle.
Corrected WAIT signal tristate timing in Write Cycle.
Corrected BER Counter Group and Stream Mapping
Addresses.
Added special requirement for using output clock at
65.536 MHz.
Added more detailed description to the DTA and WAIT
pins.
Added t
maximum values.
Added CKO0-1 and FPO0-1 setup and hold parameters for
all different clock rates.
Added this table to specify CKO0-1 jitter generation.
(1) Values of parameters t
t
(2) Separated parameter t
Added more detail to figure.
(1) Values of parameters t
t
(2) Added CKO skew parameter, t
internal APLL).
Added more detail and t
SINV,
SONV,
7
t
SIPZ
t
SOPZ
FPIS
and t
, t
and t
FPIH
SINZ
SONZ
(input frame pulse setup and hold)
are revised.
are revised.
CKOS
Change
Change
SIPS,
CKD
SOPS,
to figure.
into t
t
SIPH,
t
SOPH,
CKOS
CKDP
t
SINS,
t
, (clock source to
SONS,
and t
t
SINH,
t
CKDN.
Data Sheet
SONH,
t
SIPV,
t
SOPV,