zl50075 Zarlink Semiconductor, zl50075 Datasheet
zl50075
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zl50075 Summary of contents
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... CKi0 CK_SEL1-0 Timing FPo1-0 CKo1-0 Figure 1 - ZL50075 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of ...
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... The ZL50075 uses a master clock (CKi0) and frame pulse (FPi0) to define the TDM data stream frame boundary and timing. A high speed system clock is derived internally from CKi0 and FPi0. The input and output data streams can independently reference their timings to the input clock or to the internal system clock ...
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... Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.0 Per-Channel A-Law/m-Law Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.0 Bit Error Rate Tester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.1 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.1.1 Read Cycle 10.1.2 Write Cycle 11.0 Power-up and Initialization of the ZL50075 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11.1 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11.2 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11.3 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 12.0 IEEE 1149.1 Test Access Port 12.1 Test Access Port (TAP 12.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 12 ...
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... Block Init Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14.8 Block Init Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15.0 DC/AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ZL50075 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50075 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure Channel Basic Switch Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3 - Input and Output Data Rate Conversion Example Figure 4 - Input Sampling Point Delay Programming Figure 5 - Output Bit Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6 - Data Throughput Delay for Constant Delay Figure 7 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8 - Example PRBS Timeslot Insertion ...
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... Table 21 - BER Counter Group and Stream Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 22 - Group Control Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 23 - Group Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 24 - Input Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 25 - Output Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 26 - Block and Power-up Initialization Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ZL50075 List of Tables 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Electrical Characteristics - Serial Data Timing1 to CKo2“ 55 Figure 15 "Serial Data Timing to CKo" ZL50075 Change Clarified WAIT signal description in Read Cycle. Corrected WAIT signal tristate timing in Read Cycle. Clarified WAIT signal description in Write Cycle. Corrected WAIT signal tristate timing in Write Cycle. ...
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... Pin Diagram - ZL50075 324 Ball PBGA (as viewed through top of package) A1 corner identified by metallized marking D[15] D[14] D[5] D[4] D[3] A STOA IM D[11] D[10] D[8] B [1] STIA STIB STIA STIB STOA C [2] [1] [0] [0] [0] STOB CKO STIA STOB VDD_ D [2] [0] [1] [0] CORE STIA STIB STOB FPO ...
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... Input) This pin accepts an 8.192 MHz, 16.384 MHz, 32.678 MHz or 65.536 MHz clock. This clock must be provided for correct operation of the ZL50075. selected by the CK_SEL1-0 inputs. The active clock edge may be either rising or falling, programmed by the Input Clock Control Register (Section 14.5). ...
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... A5, D7, B8, C8 A6, A7, D9, B9, C9, A8, A9, A10, B10, C10, A11, D11, C11, B11, A12, D12, A13, B12, A14 ZL50075 Name FPi0 ST-BUS/GCI-Bus Frame Pulse Input (5 V Tolerant Input) This pin accepts the 8 kHz frame pulse which marks the frame boundary of the TDM data streams. The pulse width is nominally one CKi0 clock period (assuming ST-BUS mode) selected by the CK_SEL1-0 inputs ...
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... Microprocessor Port Bus Mode Select (5 V Tolerant Input) Control input Motorola mode 1 = Intel mode PWR Device Reset (5 V Tolerant Schmitt-Triggered Input) Asynchronous reset input used to initialize the ZL50075 Reset 1 = Normal See Section 11.0, Power-up and Initialization of the ZL50075 for detailed description of Reset state. 11 Zarlink Semiconductor Inc. Data Sheet Description ...
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... D5, D8, D15, E7, E10, E13, V DD_CORE F4, F8, F11, F14, G5, H6, H13, J14, K5, L13, L6, M4, M14, M15, N5, N8, N11, P7, P10, P13, R8, R15 ZL50075 Name TDI Test Data (5 V Tolerant Input with Internal Pull-up) Serial test data input. When not used, this input may be left unconnected. TDO Test Data (3 ...
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... Switch Operation The ZL50075 switches 64 kbps and Nx64 kbps data and voice channels from the TDM input streams, to timeslots in the TDM output streams. The device is non-blocking; all 32 K input channels can be switched through to the outputs. Any input channel can be switched to any available output channel. ...
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... The ZL50075 is a large switch with a comprehensive list of user configurable, ’per-group’ programmable features. In order to facilitate ease of use, the ZL50075 offers a simple programming model. Streams are grouped in sets of two, with each group sharing the same configured characteristics. In this way it is possible to reduce programming complexity, while still maintaining flexible ’ ...
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... The ZL50075 supports rate conversion from any input stream rate to any output stream rate. An example of ZL50075 rate conversion is given in Figure 3. The output stream rates do not have to follow the input stream rates. In this example, on the input side of the switch you can have 24 streams operating at 65.536 Mbps (24,576 channels - 24 groups with 1 stream in each group), 8 streams operating at 32 ...
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... Input Clock (CKi) and Input Frame Pulse (FPi) Timing The input timing for the ZL50075 can be set for one of four different frequencies. They can also be set for ST-BUS or GCI-Bus mode with positive or negative input. The CKi0 and FPi0 input timing must be provided in order for the device to be used ...
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... The input delay is enabled by the Input Sample Point Delay (bit the Group Control Registers (GCR0 - 31) as described in Section 14.4 on page 39. The input sampling point delay can range from 3/4 bit delay with a 1/4 bit resolution on a per group basis. ZL50075 17 Zarlink Semiconductor Inc. ...
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... Example: With a setting of 01111 the sampling point for bit 7 will be 3 1/2 bits Figure 4 - Input Sampling Point Delay Programming There are limitations when the ZL50075 is programmed to use CKi0 as the input stream clock source as opposed to the internal clock: • The granularity of the delay becomes 1/2 the selected reference clock period, or 1/4 bit, whichever is longer • ...
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... The OSBA bits in the Group Control Registers are used to set the bit-advancement for each of the corresponding serial output stream groups. Figure 5 illustrates the effect of the OSBA settings on the output timing. There are limitations when the ZL50075 is programmed to use CKi0 as the output stream clock source: • ...
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... To increase programming bandwidth, the ZL50075 has separate addressable 32 bit memory locations, called Connection Memory Least Significant Bytes (LSB), which provide direct access to the Connection Memories’ Lowest data bytes (bits four consecutive message mode channels can be set with one Connection Memory LSB access ...
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... N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 Figure 7 - Data Throughput Delay for Variable Delay ZL50075 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 ...
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... Bit Error Rate Tester The ZL50075 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output streams, resulting in 64 transmitters connected to the output streams and 64 receivers associated with the input streams. Each transmitter can generate a BER sequence with a pattern of 2 O.151). Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1 frame time (125 µ ...
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... Microprocessor Port The ZL50075 has a generic 16-bit microprocessor port that provides access to the 32-bit internal Data Memory (read access only), Connection Memory and Control Registers. D15 on the bus maps to Bit 31 and Bit 15 of the internal 32 bit memory or register, D14 maps to Bit 30 and Bit 14, etc. ...
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... In both Intel and Motorola modes, the A1 address input is used to identify the word alignment in internal memory, as shown in Table 7. Data bus word alignments are shown in Table 8. An example of byte addressing is given in Table 9. Microprocessor SIZ1 16 Bit Data Bus D15 - D15 - Don’t Care ZL50075 Memory/Register Bits 40200 Bits 31:24 (MSB) 40201 Bits 23:16 40202 Bits 15:8 40203 Bits 7:0 (LSB) ...
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... When the ZL50075 sees the CS signal go inactive high, it tri-states the data bus, D15 - 0 and the DTA, BERR and WAIT signals. However goes inactive high before DS goes inactive high, the DTA, BERR and WAIT signals are driven inactive high before they are tri-stated • ...
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... The microprocessor asserts the R/W control signal low, to signal a write cycle. It also drives the address A, data transfer size, SIZ1 - 0, and chip select logic drives the CS signal active low to select the ZL50075 • The microprocessor then drives the data bus, D15 - 0 with the data to be written, and then drives the DS signal active low, to signal the start of the bus cycle ...
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... Power-up and Initialization of the ZL50075 11.1 Device Reset and Initialization The PWR pin is used to reset the ZL50075. When this pin is low, the following functions are performed: • Asynchronously puts the microprocessor port in a reset state • Tristates all of the output streams (SToA0 - 31, SToB0 - 31) • ...
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... Register. 12.1 Test Access Port (TAP) The Test Access Port (TAP) accesses the ZL50075 test functions. The interface consists of 4 input and 1 output signal. as follows: • Test Clock (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent in the functional mode ...
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... When JTAG is not in use, this pin must be tied low for normal operation. The TAP signals are only applied when the ZL50075 is required test mode. When in normal, non-test mode, TRST must be connected low to disable the test logic. The remaining test pins may be left unconnected. ...
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... Memory Map of ZL50075 The memory map for the ZL50075 is given in Table 10. Address (Hex) 00000 - 1FFFF Connection Memory 20000 - 27FFF Connection Memory LSB 28000 - 2FFFF Data Memory: Read only; Bus error on write (BERR) 30000 - 37FFF Input BER Enable Control Memory 38000 - 3FFFF Invalid Address ...
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... The mapping of each output stream, SToAn and SToBn, depends on the programmed bit rate. The address offset range for each stream is illustrated in Table 12. Output Group Data Rate Timeslot Range 65 Mbps 32 Mbps 16 Mbps 8 Mbps Table 12 - Connection Memory Stream Address Offset at Various Output Rates ZL50075 Address Range Output (Hex) Group 000000 - 000FFF 16 001000 - 001FFF 17 ...
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... Each output channel timeslot occupies a range of 4 addresses in the Connection Memories. The timeslot address offset is illustrated in Table 13. It shows the maximum number of timeslots that a stream can have, but the actual number of timeslots available depends on the output data rates, as illustrated in Table 1 and Table 12. Table 13 - Connection Memory Timeslot Address Offset Range ZL50075 Timeslot Address Offset hex ...
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... V/D Voice/Data Control When this bit is low, the corresponding channel is for voice. When this bit is high, the corresponding channel is for data ICL1 - 0 Input Coding Law ICL1 - Table 14 - Connection Memory Bits (CMB) ZL50075 ICL OCL OCL ...
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... Access to this memory space is big-endian, with the most significant bytes on the data bus accessing the lower address of the connection memory. Addressing into each of the streams is illustrated in Table 15. ZL50075 ...
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... Within each stream group, the mapping of each of the actual output streams, SToAn and SToBn, depends on the output rate programmed into the Group Control Registers. The address offsets to these control areas for each of the output streams are illustrated in Table 16. ZL50075 Address Range Output ...
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... Group Control Registers. The address offsets to these data areas for each of the input streams are illustrated in Table 18. Input Group Data Rate Time-slot Range 65 Mbps 32 Mbps 16 Mbps 8 Mbps Table 18 - Data Memory Stream Address Offset at Various Output Rates ZL50075 Address Range Input (Hex) Group 028000 - 0283FF 16 028400 - 0287FF ...
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... Each byte location of the BER Enable Memory contains one read/write BER counter enable (BCE) bit, mapped into the D0 location. If the BCE bit is set, then the BER counter for the corresponding stream and timeslot is enabled for the duration of that timeslot. If the BCE bit is cleared the counter is disabled. ZL50075 Address Range Input ...
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... If the number of bit errors detected exceeds 65535 (decimal), the counter will hold that value until it is cleared. BER Input Group BER Input Stream STiA31 STiB31 Table 21 - BER Counter Group and Stream Address Mapping ZL50075 Input Streams 0 - 1023 STiAn STiBn 0 - 511 STiAn STiBn 0 - 255 STiAn STiBn N/A BERR 0 - 127 ...
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... Group Control Registers The ZL50075 addresses the issues of a simple programming model and automatic stream configuration by defining a basic switching bit rate of 65.536 Mbps and by grouping the I/O streams. Each TDM I/O group contains 2 input and 2 output streams. The 2 input streams in the same group have identical input characteristics, and similarly, the 2 output streams in the same group have identical output characteristics ...
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... Input Stream Inversion For normal operation, this bit is set low. To invert the input stream, set this bit high ISPD4 - 0 Input Sampling Point Delay Default Sampling Point is 3/4. Adjust according to Figure on page 18. Table 23 - Group Control Register (continued) ZL50075 OSBA ...
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... Otherwise, the data rate cannot exceed the selected clock source’s rate ISSRC1 - 0 Input Stream Clock Source Select ISSRC1 - 0 Table 23 - Group Control Register (continued) The Group Control Register is a static control register. Changes to bit settings may disrupt data flow on the selected port for a maximum of 2 frames. ZL50075 OSBA ...
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... When this bit is low, FPi0 is set for active high. When this bit is high, FPi0 is set for active low. 0 CKIPOL0 Clock Polarity Selection for CKi0 When this bit is low, CKi0 is set for the positive clock edge. When this bit is high, CKi0 is set for the negative clock edge. ZL50075 ...
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... The output clock rate can not exceed the selected clock source rate. All rates are avail able when the internal system clock is selected as clock source. CKO1RATE1 - CKO1 Output Clock Source for CKo1 and FPo1 SRC CKO1SRC1 - 0 Table 25 - Output Clock Control Register ZL50075 ...
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... CKO0RATE1 - CKO0 Output Clock Source for CKo0 and FPo0 SRC CKO0SRC1 - Table 25 - Output Clock Control Register (continued) ZL50075 ...
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... Table 26 - Block and Power-up Initialization Status Bits Any access to the connection memory or the data memory during a block initialization or a reset initialization will result in a bus error, BERR. All TDM outputs are tri-stated during any block initialization. ZL50075 H Description 0 if Block initialization is completed; ...
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... Recommended Operating Conditions - Characteristics 1 Operating Temperature 2 Positive Supply Core 3 Positive Supply I/O 4 Input Voltage (non-5 V tolerant inputs) 5 Input Voltage (5 V tolerant inputs) Note 1: Typical figures are at 25°C, V DD_CORE subject to production testing. ZL50075 ) unless otherwise stated SS Sym. Min. V -0.5 DD_IO V -0.5 DD_CORE V -0.5 I_3V V -0.5 I_5V ...
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... AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels - (V ) unless otherwise stated. SS Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low 1. Characteristics are over recommended operating conditions unless otherwise stated. ZL50075 1 Sym. Min. Typ. Max. I 500 DD_CORE I 62 DD_IO I 105 ...
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... When using internal APLL clock source and the CKi0 frequency is less than or equal to the data rate. Note 4: When using input clock source CKi0 instead of the internal APLL clock source. Note 5: When using internal APLL clock source and the CKi0 frequency is higher than or equal to twice the data rate. ZL50075 2 Sym. Min. Typ. ...
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... ZL50075 t FPIW FPi t t FPIS FPH CKi Input Frame Boundary Figure 11 - Frame Pulse Input and Clock Input Zarlink Semiconductor Inc. t CKIP t t CKIH CKIL t t rCKI fCKI 49 Data Sheet ...
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... DD_CORE subject to production testing. Note 3: CKo clock source set to internal 131 MHz APLL, and CKi0 and FPi0 meet all the timing requirements. Note 4: When CKo source is set to one of the CKi/FPi, its output timings directly follow its source. ZL50075 2 Sym. Min. Typ ...
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... Jitter at CKO0-1 (32.768 MHz) 4 Jitter at CKO0-1 (65.536 MHz) Note 1: CKi at 8 MHz, output clock source set to internal APLL. No jitter presented on the the Cki0 input. Note 2: For 65.536 MHz output clock, the total loading on the output should not be larger than 10pF. ZL50075 t FPOH t CKOP t FPOH ...
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... All of these specifications refer to ST-BUS inputs and outputs with clock source set to CKi. Note 3: Typical figures are at 25°C, V DD_CORE subject to production testing. Note 4: Loads on all serial outputs set to 30 pF. Note 5: High Impedance is measured by pulling to the appropriate rail with ZL50075 2 to CKi 3 Sym. Min. Typ. Max. t 3.5 8 CKDP 4 ...
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... Note 1 : CKi frequency is assumed to be twice of the STin data rate, so that the sampling point is at the 3/4 point of the bit cell 1/2 clock period after the active clock edge Note CKi frequency is the same as the STin data rate, the sampling point moves to the 1/2 point of the bit cell, or 1/2 clock period after the active clock edge. ZL50075 t CKDN t ...
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... Data Capture points vary with respect to CKo edge depending on clock rates & fractional delay settings. Note 2: All of these specifications refer to ST-BUS inputs, ST-BUS outputs and CKo outputs set to internal clock source. Note 3: Typical figures are at 25°C, V DD_CORE subject to production testing. Note 4: Loads on all serial outputs set to 30 pF. ZL50075 CKo 3 Sym. Min. Typ ...
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... Note 1 : CKo frequency is assumed to be twice of the STin data rate, so that the sampling point is at the 3/4 point of the bit cell 1/2 clock period after the active clock edge Note CKo frequency is the same as the STin data rate, the sampling point moves to the 1/2 point of the bit cell, or 1/2 clock period after the active clock edge. ZL50075 t CKOS t ...
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... CS deasserted to WAIT tri-stated UDS/LDS skew UDS/LDS to DS set-up Note 1: Typical figures are at 25°C, V DD_CORE subject to production testing. Note 2: High Impedance is measured by pulling to the appropriate rail with ZL50075 Sym. Min. Typ DSRE t 0 CSRE t 0 CSS t 0 ...
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... DS t CSRE CS A18-A0 RWN,SIZ D31-D0 READ D31-D0 WRITE Hi-Z DTA BERR Hi-Z WAIT Figure 16 - Microprocessor Bus Interface Timing DS SIZ1-SIZ0 (BE1-BE0 or UDS, LDS) ZL50075 t DSRE t CSS t ADS VALID VALID READ DATA t WDS VALID WRITE DATA t DSR t AKD t CSWA t WDD t DSRE t BEDS t DSK Figure 17 - Intel Mode Timing 57 Zarlink Semiconductor Inc ...
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... Characteristics are over recommended operating conditions unless otherwise stated. Note 2: Typical figures are at 25°C, V DD_CORE subject to production testing. TCK t TMSS TMS t TDIS TDi TDo TRST PWR Figure 18 - IEEE 1149.1 Test Port & PWR Reset Timing ZL50075 Sym. Min. Typ. t 100 TCKP t TCKF t 20 TCKH t 20 TCKL t ...
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... Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE ACN 15 Jul 03 DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...