zl50075 Zarlink Semiconductor, zl50075 Datasheet - Page 27

• Manufacturer Part Number: zl50075
• Description: 32 K Channel Digital Switch With High Jitter Tolerance, Rate Conversion Per Group Of 2 Streams 8, 16, 32 Or 64 Mbps , And 64 Inputs And 64 Outputs
• Manufacturer: Zarlink Semiconductor

11.0
11.1
The PWR pin is used to reset the ZL50075. When this pin is low, the following functions are performed:
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11.2
The ZL50075 has two separate power supplies: V
power-up sequence is for V
V
11.3
Upon power up, the ZL50075 should be initialized as follows:
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DD_IO
Asynchronously puts the microprocessor port in a reset state
Tristates all of the output streams (SToA0 - 31, SToB0 - 31)
Preloads all of the registers with their default values (refer to the individual registers for default values)
Clears all internal counters
Assert PWR to low immediately after power is applied
Set the TRST pin low to disable the JTAG TAP controller
Deassert the PWR pin.
Apply the Master Clock Input (CKi0) and Master Frame Pulse Input (FPi0) to the values defined by the
CK_SEL1 - 0 pins
Set the ODE pin low to disable the output streams
Device Reset and Initialization
Power Supply Sequencing
supply by more than 0.3 V. Both supplies may be powered-down simultaneously.
Initialization
Power-up and Initialization of the ZL50075
Address
SIZ1 - 0
BERR
WAIT
Data
DTA
R/W
CS
DS
The cycle termination signals WAIT & DTA are provided for all bus configurations.
Hi-Z
DD_IO
Hi-Z
to be applied first, followed by the V
Figure 10 - Write Cycle Operation
Zarlink Semiconductor Inc.
ZL50075
DD_IO
27
(3.3 V) and V
DD_CORE
DD_CORE
supply. V
(1.8 V). The recommended
Hi-Z
DD_CORE
should not lead
Data Sheet