zl50075 Zarlink Semiconductor, zl50075 Datasheet - Page 28

• Manufacturer Part Number: zl50075
• Description: 32 K Channel Digital Switch With High Jitter Tolerance, Rate Conversion Per Group Of 2 Streams 8, 16, 32 Or 64 Mbps , And 64 Inputs And 64 Outputs
• Manufacturer: Zarlink Semiconductor

Note: After the PWR reset is removed, and on the application of a suitable master clock input, it takes
approximately 1 ms for the internal initialization to complete
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Note: If the master clock input, CKi0, is not available, the microprocessor port will assert BERR on all accesses and
read cycles.
12.0
The JTAG test port is implemented to meet the mandatory requirements of the IEEE 1149.1 (JTAG) standard. The
operation of the boundary-scan circuity is controlled by an external Test Access Port (TAP) Controller.
The ZL50075 uses the public instructions defined in IEEE 1149.1, with the provision of a 16-bit Instruction Register,
and three scannable Test Data Registers: Boundary Scan Register, Bypass Register and Device Identification
Register.
12.1
The Test Access Port (TAP) accesses the ZL50075 test functions. The interface consists of 4 input and 1 output
signal. as follows:
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Automatic block initialization of the Connection Memory to all zeros occurs, without microprocessor
intervention
All Group Control Registers are preset to 000C000C hex, corresponding to rates of 65 Mbps, no link
inversions, no fractional output bit advancements, internal clock source, and no input sample point delays
The Input Clock Control Register is preset to 0DB hex, corresponding to:
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The Output Clock Control Register is pre-set to 060D1C3C hex, corresponding to:
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Test Clock (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any on-chip
clock and thus remains independent in the functional mode. The TCK permits shifting of test data into or out
of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with
the on-chip logic.
Test Mode Select (TMS) - The TAP Controller uses the logic signals received at the TMS input to control
test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally
pulled to V
Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. Both registers are
described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses.
This pin is internally pulled to V
Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or data register are serially shifted out towards the TDo. The data out of the
TDo is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan
cells, the TDo driver is set to a high impedance state.
All clock inputs set to negative logic sense
All frame pulse inputs set to negative logic sense
All input frame pulses set to ST-BUS timing
All clock outputs set to negative logic sense
All frame pulse outputs set to negative logic sense
All output frame pulses set to ST-BUS timing
All output clock source selections to internal
Clock outputs, CKo0 - 1 are preset to rates of 65 MHz and 32 MHz, respectively
Test Access Port (TAP)
IEEE 1149.1 Test Access Port
DD_IO
when it is not driven from an external source.
DD_IO
when it is not driven from an external source.
Zarlink Semiconductor Inc.
ZL50075
28
Data Sheet