zl50075 Zarlink Semiconductor, zl50075 Datasheet - Page 42

• Manufacturer Part Number: zl50075
• Description: 32 K Channel Digital Switch With High Jitter Tolerance, Rate Conversion Per Group Of 2 Streams 8, 16, 32 Or 64 Mbps , And 64 Inputs And 64 Outputs
• Manufacturer: Zarlink Semiconductor

14.5
The Input Clock Control Register is used to select the logic sense of the input clock.
31 - 9
8 - 3
External Read/Write Address: 40280
Reset Value: 0DB
Bit
31
15
2
1
0
0
0
Input Clock Control Register
30
14
0
0
GCISEL0
CKIPOL0
FPIPOL0
Unused
Unused
Name
H
29
13
0
0
28
12
Reserved. In normal functional mode, these bits MUST be set to zero.
Reserved. In normal functional mode, these bits MUST be set to 011011.
GCI-Bus Selection for FPi0
When this bit is low, FPi0 is set for ST-BUS mode.
When this bit is high, FPi0 is set for GCI-Bus mode.
Frame Pulse Polarity Selection for FPi0
When this bit is low, FPi0 is set for active high.
When this bit is high, FPi0 is set for active low.
Clock Polarity Selection for CKi0
When this bit is low, CKi0 is set for the positive clock edge.
When this bit is high, CKi0 is set for the negative clock edge.
0
0
27
11
0
0
H
Table 24 - Input Clock Control Register
26
10
0
0
25
0
9
0
Zarlink Semiconductor Inc.
ZL50075
24
8
0
0
42
23
7
0
1
Description
22
0
6
1
21
0
5
0
20
0
4
1
19
0
3
1
SEL0
GCI
18
0
2
POL0
FPI
Data Sheet
17
0
1
POL0
CKI
16
0
0