zl50075 Zarlink Semiconductor, zl50075 Datasheet - Page 16

• Manufacturer Part Number: zl50075
• Description: 32 K Channel Digital Switch With High Jitter Tolerance, Rate Conversion Per Group Of 2 Streams 8, 16, 32 Or 64 Mbps , And 64 Inputs And 64 Outputs
• Manufacturer: Zarlink Semiconductor

2.0
The input timing for the ZL50075 can be set for one of four different frequencies. They can also be set for ST-BUS
or GCI-Bus mode with positive or negative input. The CKi0 and FPi0 input timing must be provided in order for the
device to be used. CKi0 is used to generate the internal clock. This clock is used for all the internal logic and can be
used as one of the clocks that defines the timing for the input and output data. The input stream clock source is
selected by the ISSRC1 - 0 (bits 1 - 0) in the Group Control Register. The output stream clock source is selected by
the OSSRC1 - 0 (bits 17 - 16) in the Group Control Register.
The CKi0 and FPi0 input frequency is set via the CK_SEL1 - 0 pins as shown in Table 3. By default the CKi0 and
FPi0 pins accept ST-BUS, negative input timing. The input frame pulse format (ST-BUS/GCI-Bus), frame pulse
polarity, and clock polarity can be programmed by the GCISEL0 (bit 2), FPIPOL0 (bit 1), and CKIPSL0 (bit 0) in the
Input Clock Control Register (ICCR), as described in Section 14.5.
The input streams, output streams, and output clocks / frame pulses can use either the internal system clock or the
input CKi0 and FPi0 as clock sources. The input streams’ clock sources are controlled by the ISSRC1-0 (bits 1 - 0)
in the Group Control Registers (GCR). The output streams’ clock sources are controlled by the OSSRC1-0 (bits 17
- 16) in the Group Control Registers (GCR). The output clocks’ / frame pulses’ clock sources are controlled by the
CKO1SRC1-0 (bits 8-7) and CKO0SRC1-0 (bits 1-0) in the Output Clock Control Register (OCCR). Using the input
CKi0 and FPi0 as clock source provides a direct interface to jittery peripherals, while using the internal system clock
as clock source provides the best data rate and clock rate flexibility.
Output Groups 30 - 31 at 8 Mbps
Example:
Input Groups 0 - 23 at 65 Mbps; Output Groups 0 - 14 at 65 Mbps
Input Groups 24 - 27 at 32 Mbps; Output Groups 15 - 28 at 32 Mbps
Input Groups 28 - 31 at 16 Mbps; Output Group 29 at 16 Mbps
Input Clock (CKi) and Input Frame Pulse (FPi) Timing
28 - 31 at 16 Mbps
24 - 27 at 32 Mbps
0 - 23 at 65 Mbps
Input Groups
Input Groups
Input Groups
Figure 3 - Input and Output Data Rate Conversion Example
CK_SEL1
STiA24 - 27 at 32 Mbps
STiB24 - 27 at 32 Mbps
STiA28 - 31 at 16 Mbps
STiB28 - 31 at 16 Mbps
STiA0 - 23 at 65 Mbps
STiB0 - 23 Not Active
Table 3 - CKi0 and FPi0 Setting via CK_SEL1 - 0
0
0
1
1
Zarlink Semiconductor Inc.
CK_SEL0
ZL50075
0
1
0
1
16
Input CKi0 and FPi0
SToA15 - 28 at 32 Mbps
SToB15 - 28 at 32 Mbps
SToA0 - 14 at 65 Mbps
SToB0 - 14 Not Active
SToA30 - 31 at 8 Mbps
SToB30 - 31 at 8 Mbps
16.384 MHz
32.768 MHz
65.536 MHz
8.192 MHz
SToA29 at 16 Mbps
SToB29 at 16 Mbps
15 - 28 at 32 Mbps
0 - 14 at 65 Mbps
Output Groups
29 at 16 Mbps
30 - 31 at 8 Mbps
Output Group
Output Groups
Output Groups
Data Sheet