zl50075 Zarlink Semiconductor, zl50075 Datasheet - Page 30

• Manufacturer Part Number: zl50075
• Description: 32 K Channel Digital Switch With High Jitter Tolerance, Rate Conversion Per Group Of 2 Streams 8, 16, 32 Or 64 Mbps , And 64 Inputs And 64 Outputs
• Manufacturer: Zarlink Semiconductor

13.0
The memory map for the ZL50075 is given in Table 10.
14.0
This section describes all the memories and registers that are used in this device.
14.1
Address range 00000 - 1FFFF hex.
On power-up, all Connection Memory locations are initialized automatically to 00000000 hex, using the Block
Initialization feature, as described in Section 14.7 and Section 14.8.
The 32 bit Connection Memory has 32,768 locations. Each 32 bit long-word is used to program the desired source
data and any other per-channel characteristics of one output time-slot.
The memory map for the Connection Memory is sub-divided into 32 blocks, each corresponding to one of the
possible 32 output stream group numbers. The address ranges for these blocks are illustrated in Table 11.
Address (Hex)
00000 - 1FFFF
28000 - 2FFFF
38000 - 3FFFF
4028C - 4028F
20000 - 27FFF
30000 - 37FFF
40000 - 401FF
40288 - 4028B
40200 - 4027F
40280 - 40283
40284 - 40287
40290- 7FFFF
Connection Memory
Memory Map of ZL50075
Detailed Memory and Register Descriptions
Connection Memory
Connection Memory LSB
Data Memory: Read only; Bus error on write (BERR)
Input BER Enable Control Memory
Invalid Address. Access causes Bus error (BERR)
BER Counters
Group Control Registers
Input Clock Control Register
Output Clock Control Register
Block Init Register
Block Init Enable
Invalid Address. Access causes Bus error (BERR)
Table 10 - Memory Map
Zarlink Semiconductor Inc.
ZL50075
30
Description
Data Sheet